Lines Matching +full:0 +full:- +full:3

2  * QEMU model of the Clock-Reset-LPD (CRL).
5  * SPDX-License-Identifier: GPL-2.0-or-later
14 #include "target/arm/cpu-qom.h"
16 #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl"
19 REG32(ERR_CTRL, 0x0)
20     FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
21 REG32(IR_STATUS, 0x4)
22     FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
23 REG32(IR_MASK, 0x8)
24     FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
25 REG32(IR_ENABLE, 0xc)
26     FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
27 REG32(IR_DISABLE, 0x10)
28     FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
29 REG32(WPROT, 0x1c)
30     FIELD(WPROT, ACTIVE, 0, 1)
31 REG32(PLL_CLK_OTHER_DMN, 0x20)
32     FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
33 REG32(RPLL_CTRL, 0x40)
34     FIELD(RPLL_CTRL, POST_SRC, 24, 3)
35     FIELD(RPLL_CTRL, PRE_SRC, 20, 3)
38     FIELD(RPLL_CTRL, BYPASS, 3, 1)
39     FIELD(RPLL_CTRL, RESET, 0, 1)
40 REG32(RPLL_CFG, 0x44)
45     FIELD(RPLL_CFG, RES, 0, 4)
46 REG32(RPLL_FRAC_CFG, 0x48)
48     FIELD(RPLL_FRAC_CFG, SEED, 22, 3)
51     FIELD(RPLL_FRAC_CFG, DATA, 0, 16)
52 REG32(PLL_STATUS, 0x50)
54     FIELD(PLL_STATUS, RPLL_LOCK, 0, 1)
55 REG32(RPLL_TO_XPD_CTRL, 0x100)
58 REG32(LPD_TOP_SWITCH_CTRL, 0x104)
62     FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
63 REG32(LPD_LSBUS_CTRL, 0x108)
66     FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3)
67 REG32(CPU_R5_CTRL, 0x10c)
73     FIELD(CPU_R5_CTRL, SRCSEL, 0, 3)
74 REG32(IOU_SWITCH_CTRL, 0x114)
77     FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3)
78 REG32(GEM0_REF_CTRL, 0x118)
83     FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3)
84 REG32(GEM1_REF_CTRL, 0x11c)
89     FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3)
90 REG32(GEM_TSU_REF_CTRL, 0x120)
93     FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3)
94 REG32(USB0_BUS_REF_CTRL, 0x124)
97     FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3)
98 REG32(UART0_REF_CTRL, 0x128)
101     FIELD(UART0_REF_CTRL, SRCSEL, 0, 3)
102 REG32(UART1_REF_CTRL, 0x12c)
105     FIELD(UART1_REF_CTRL, SRCSEL, 0, 3)
106 REG32(SPI0_REF_CTRL, 0x130)
109     FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3)
110 REG32(SPI1_REF_CTRL, 0x134)
113     FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3)
114 REG32(CAN0_REF_CTRL, 0x138)
117     FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3)
118 REG32(CAN1_REF_CTRL, 0x13c)
121     FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3)
122 REG32(I2C0_REF_CTRL, 0x140)
125     FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3)
126 REG32(I2C1_REF_CTRL, 0x144)
129     FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3)
130 REG32(DBG_LPD_CTRL, 0x148)
133     FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3)
134 REG32(TIMESTAMP_REF_CTRL, 0x14c)
137     FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
138 REG32(CRL_SAFETY_CHK, 0x150)
139 REG32(PSM_REF_CTRL, 0x154)
141     FIELD(PSM_REF_CTRL, SRCSEL, 0, 3)
142 REG32(DBG_TSTMP_CTRL, 0x158)
145     FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
146 REG32(CPM_TOPSW_REF_CTRL, 0x15c)
149     FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3)
150 REG32(USB3_DUAL_REF_CTRL, 0x160)
153     FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3)
154 REG32(RST_CPU_R5, 0x300)
158     FIELD(RST_CPU_R5, RESET_CPU0, 0, 1)
159 REG32(RST_ADMA, 0x304)
160     FIELD(RST_ADMA, RESET, 0, 1)
161 REG32(RST_GEM0, 0x308)
162     FIELD(RST_GEM0, RESET, 0, 1)
163 REG32(RST_GEM1, 0x30c)
164     FIELD(RST_GEM1, RESET, 0, 1)
165 REG32(RST_SPARE, 0x310)
166     FIELD(RST_SPARE, RESET, 0, 1)
167 REG32(RST_USB0, 0x314)
168     FIELD(RST_USB0, RESET, 0, 1)
169 REG32(RST_UART0, 0x318)
170     FIELD(RST_UART0, RESET, 0, 1)
171 REG32(RST_UART1, 0x31c)
172     FIELD(RST_UART1, RESET, 0, 1)
173 REG32(RST_SPI0, 0x320)
174     FIELD(RST_SPI0, RESET, 0, 1)
175 REG32(RST_SPI1, 0x324)
176     FIELD(RST_SPI1, RESET, 0, 1)
177 REG32(RST_CAN0, 0x328)
178     FIELD(RST_CAN0, RESET, 0, 1)
179 REG32(RST_CAN1, 0x32c)
180     FIELD(RST_CAN1, RESET, 0, 1)
181 REG32(RST_I2C0, 0x330)
182     FIELD(RST_I2C0, RESET, 0, 1)
183 REG32(RST_I2C1, 0x334)
184     FIELD(RST_I2C1, RESET, 0, 1)
185 REG32(RST_DBG_LPD, 0x338)
189     FIELD(RST_DBG_LPD, RESET, 0, 1)
190 REG32(RST_GPIO, 0x33c)
191     FIELD(RST_GPIO, RESET, 0, 1)
192 REG32(RST_TTC, 0x344)
193     FIELD(RST_TTC, TTC3_RESET, 3, 1)
196     FIELD(RST_TTC, TTC0_RESET, 0, 1)
197 REG32(RST_TIMESTAMP, 0x348)
198     FIELD(RST_TIMESTAMP, RESET, 0, 1)
199 REG32(RST_SWDT, 0x34c)
200     FIELD(RST_SWDT, RESET, 0, 1)
201 REG32(RST_OCM, 0x350)
202     FIELD(RST_OCM, RESET, 0, 1)
203 REG32(RST_IPI, 0x354)
204     FIELD(RST_IPI, RESET, 0, 1)
205 REG32(RST_SYSMON, 0x358)
207     FIELD(RST_SYSMON, CFG_RST, 0, 1)
208 REG32(RST_FPD, 0x360)
210     FIELD(RST_FPD, POR, 0, 1)
211 REG32(PSM_RST_MODE, 0x370)
213     FIELD(PSM_RST_MODE, RST_MODE, 0, 2)