| #
7698afc4 |
| 02-Jul-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-target-arm-20250701-1' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
* MAINTAINERS update for arm hvf
* target/arm: Make RETA[AB] UNDEF when pauth is not implemen
Merge tag 'pull-target-arm-20250701-1' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
* MAINTAINERS update for arm hvf
* target/arm: Make RETA[AB] UNDEF when pauth is not implemented
* target/arm: Refactoring of ID register value storage
* target/arm: Various refactoring/cleanup patches
* virt: Don't show an ITS in ACPI tables when no ITS is present
* tests/functional: test device passthrough on aarch64
* tests/functional: Expand Aarch64 SMMU tests to run on HVF accelerator
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# gpg: Signature made Tue 01 Jul 2025 12:59:30 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250701-1' of https://gitlab.com/pm215/qemu: (43 commits)
tests/functional: test device passthrough on aarch64
tests/functional: Expand Aarch64 SMMU tests to run on HVF accelerator
tests/functional: Add hvf_available() helper
tests/functional: Require TCG to run Aarch64 imx8mp-evk test
tests/functional: Restrict nested Aarch64 Xen test to TCG
tests/functional: Set sbsa-ref machine type in each test function
hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition
hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized()
hw/arm/virt: Make EL2 accelerator check an accept-list
hw/arm/virt: Make EL3-guest accel check an accept-list
target/arm: Restrict system register properties to system binary
target/arm/hvf: Pass @target_el argument to hvf_raise_exception()
target/arm: Correct KVM & HVF dtb_compatible value
target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event
accel/hvf: Trace VM memory mapping
target/arm/hvf: Trace hv_vcpu_run() failures
target/arm/hvf: Directly re-lock BQL after hv_vcpu_run()
target/arm: Unify gen_exception_internal()
target/arm: Reduce arm_cpu_post_init() declaration scope
target/arm: Remove arm_handle_psci_call() stub
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
| #
a2e3508a |
| 01-Jul-2025 |
Eric Auger <eric.auger@redhat.com> |
arm/cpu: Add sysreg definitions in cpu-sysregs.h
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be
arm/cpu: Add sysreg definitions in cpu-sysregs.h
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named fields in isar struct to an array cell.
[CH: reworked to use different structures]
[CH: moved accessors from the patches first using them to here,
dropped interaction with writable registers, which will happen
later]
[CH: use DEF magic suggested by rth]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20250617153931.1330449-2-cohuck@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|