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64c9e297 |
| 14-May-2012 |
Andreas Färber <afaerber@suse.de> |
vexpress: Use cpu_arm_init() to obtain ARMCPU
Needed for arm_pic_init_cpu().
Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Peter Maydell <peter.maydell@linaro.org>
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5ae93306 |
| 14-Mar-2012 |
Andreas Färber <afaerber@suse.de> |
arm hw/: Don't use CPUState
Scripted conversion: for file in hw/arm-misc.h hw/arm_boot.c hw/arm_pic.c hw/armv7m.c hw/exynos4210.h hw/highbank.c hw/integratorcp.c hw/musicpal.c hw/omap.h hw/pxa.h h
arm hw/: Don't use CPUState
Scripted conversion: for file in hw/arm-misc.h hw/arm_boot.c hw/arm_pic.c hw/armv7m.c hw/exynos4210.h hw/highbank.c hw/integratorcp.c hw/musicpal.c hw/omap.h hw/pxa.h hw/pxa2xx_gpio.c hw/pxa2xx_pic.c hw/realview.c hw/strongarm.h hw/versatilepb.c hw/vexpress.c hw/xilinx_zynq.c ; do sed -i "s/CPUState/CPUARMState/g" $file done
Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
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961f195e |
| 16-Feb-2012 |
Peter Maydell <peter.maydell@linaro.org> |
hw/vexpress.c: Add vexpress-a15 machine
Add the vexpress-a15 machine, and the A-Series memory map it uses.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaer
hw/vexpress.c: Add vexpress-a15 machine
Add the vexpress-a15 machine, and the A-Series memory map it uses.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
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96eacf64 |
| 16-Feb-2012 |
Peter Maydell <peter.maydell@linaro.org> |
arm_boot: Pass base address of GIC CPU interface, not whole GIC
The arm_boot secondary boot loader code needs the address of the GIC CPU interface. Obtaining this from the base address of the privat
arm_boot: Pass base address of GIC CPU interface, not whole GIC
The arm_boot secondary boot loader code needs the address of the GIC CPU interface. Obtaining this from the base address of the private peripheral region was possible for A9 and 11MPcore, but the A15 puts the GIC CPU interface in a different place. So make boards pass in the GIC CPU interface address directly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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b7206878 |
| 16-Feb-2012 |
Peter Maydell <peter.maydell@linaro.org> |
hw/vexpress.c: Instantiate the motherboard CLCD
Instantiate the CLCD on the vexpress motherboard as well as one on the daughterboard -- the A15 daughterboard does not have a CLCD and so relies on th
hw/vexpress.c: Instantiate the motherboard CLCD
Instantiate the CLCD on the vexpress motherboard as well as one on the daughterboard -- the A15 daughterboard does not have a CLCD and so relies on the motherboard one.
At the moment QEMU doesn't provide infrastructure for selecting which display device gets to actually show graphics -- the first one registered is it. Fortunately this works for the major use case (Linux): if the daughterboard has a CLCD it will come first and be used, otherwise we fall back to the motherboard CLCD. So we don't (currently) need to implement the control register which allows software to tell the mux which video output to pass through to the outside world.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
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4c3b29b8 |
| 16-Feb-2012 |
Peter Maydell <peter.maydell@linaro.org> |
hw/vexpress.c: Factor out daughterboard-specific initialization
Factor out daughterboard specifics into a data structure and daughterboard initialization function, in preparation for adding vexpress
hw/vexpress.c: Factor out daughterboard-specific initialization
Factor out daughterboard specifics into a data structure and daughterboard initialization function, in preparation for adding vexpress-a15 support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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aac1e02c |
| 16-Feb-2012 |
Peter Maydell <peter.maydell@linaro.org> |
hw/vexpress.c: Move secondary CPU boot code to SRAM
On real Versatile Express hardware, the boot ROM puts the secondary CPU bootcode/holding pen in SRAM. We can therefore rely on Linux not trashing
hw/vexpress.c: Move secondary CPU boot code to SRAM
On real Versatile Express hardware, the boot ROM puts the secondary CPU bootcode/holding pen in SRAM. We can therefore rely on Linux not trashing this memory until secondary CPUs have booted up, and can put our QEMU-specific pen code in the same place. This allows us to drop the odd "hack" RAM page we were using before.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2558e0a6 |
| 16-Feb-2012 |
Peter Maydell <peter.maydell@linaro.org> |
hw/vexpress.c: Make motherboard peripheral memory map table-driven
Pull the addresses used for mapping motherboard peripherals into memory out into a table. This will allow us to simply provide a se
hw/vexpress.c: Make motherboard peripheral memory map table-driven
Pull the addresses used for mapping motherboard peripherals into memory out into a table. This will allow us to simply provide a second table to implement the "Cortex-A Series" memory map used by the A15 variant of Versatile Express, as well as the current "Legacy" map used by A9.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
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7a65c8cc |
| 09-Feb-2012 |
Peter Maydell <peter.maydell@linaro.org> |
ARM devboards: Set arm_sysctl properties before init, not after
The ARM devboard models (vexpress-a9, realview, versatilepb, etc) were accidentally trying to set one of the arm_sysctl properties aft
ARM devboards: Set arm_sysctl properties before init, not after
The ARM devboard models (vexpress-a9, realview, versatilepb, etc) were accidentally trying to set one of the arm_sysctl properties after device init. This has now become a fatal error; set the property before device init where it should be done instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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5a157588 |
| 17-Jan-2012 |
Peter Maydell <peter.maydell@linaro.org> |
vexpress, realview: Add (dummy) L2 cache controller
Instantiate the L2 cache controller on the ARM devboards which have one, since we have a dummy model of it now. Note that the only non-MP board wi
vexpress, realview: Add (dummy) L2 cache controller
Instantiate the L2 cache controller on the ARM devboards which have one, since we have a dummy model of it now. Note that the only non-MP board with an L2x0 is the PB1176, which we don't model.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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078758d0 |
| 13-Jan-2012 |
Evgeny Voevodin <e.voevodin@samsung.com> |
hw/arm_boot.c: Make SMP boards specify address to poll in bootup loop
The secondary CPU bootloader in arm_boot.c holds secondary CPUs in a pen until the primary CPU releases them. Make boards specif
hw/arm_boot.c: Make SMP boards specify address to poll in bootup loop
The secondary CPU bootloader in arm_boot.c holds secondary CPUs in a pen until the primary CPU releases them. Make boards specify the address to be polled to determine whether to leave the pen (it was previously hardcoded to 0x10000030, which is a Versatile Express/ Realview specific system register address).
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
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6b620ca3 |
| 13-Jan-2012 |
Paolo Bonzini <pbonzini@redhat.com> |
prepare for future GPLv2+ relicensing
All files under GPLv2 will get GPLv2+ changes starting tomorrow. event_notifier.c and exec-obsolete.h were only ever touched by Red Hat employees and can be rel
prepare for future GPLv2+ relicensing
All files under GPLv2 will get GPLv2+ changes starting tomorrow. event_notifier.c and exec-obsolete.h were only ever touched by Red Hat employees and can be relicensed now.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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c5705a77 |
| 20-Dec-2011 |
Avi Kivity <avi@redhat.com> |
vmstate, memory: decouple vmstate from memory API
Currently creating a memory region automatically registers it for live migration. This differs from other state (which is enumerated in a VMStateDe
vmstate, memory: decouple vmstate from memory API
Currently creating a memory region automatically registers it for live migration. This differs from other state (which is enumerated in a VMStateDescription structure) and ties the live migration code into the memory core.
Decouple the two by introducing a separate API, vmstate_register_ram(), for registering a RAM block for migration. Currently the same implementation is reused, but later it can be moved into a separate list, and registrations can be moved to VMStateDescription blocks.
Signed-off-by: Avi Kivity <avi@redhat.com>
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e6d17b05 |
| 05-Oct-2011 |
Avi Kivity <avi@redhat.com> |
vexpress: convert to memory API
Signed-off-by: Avi Kivity <avi@redhat.com>
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03a0e944 |
| 28-Oct-2011 |
Peter Maydell <peter.maydell@linaro.org> |
hw/vexpress.c, hw/realview.c: Add PL041 to VExpress, Realview boards
Instantiate the PL041 audio on the Versatile Express and Realview board models.
Signed-off-by: Peter Maydell <peter.maydell@lina
hw/vexpress.c, hw/realview.c: Add PL041 to VExpress, Realview boards
Instantiate the PL041 audio on the Versatile Express and Realview board models.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
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acb9b722 |
| 22-Jul-2011 |
Peter Maydell <peter.maydell@linaro.org> |
vexpress, realview: Use pl111, not pl110
The Versatile Express, Realview EB, PBX A9 and PB A8 boards all use a PL111 for their graphics, not a PL110. Now we model the PL111, use it on these board mo
vexpress, realview: Use pl111, not pl110
The Versatile Express, Realview EB, PBX A9 and PB A8 boards all use a PL111 for their graphics, not a PL110. Now we model the PL111, use it on these board models.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2055283b |
| 07-Mar-2011 |
Peter Maydell <peter.maydell@linaro.org> |
hw/vexpress.c: Add model of ARM Versatile Express board
Add a model of the ARM Versatile Express board (with A9MPx4 daughterboard).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-of
hw/vexpress.c: Add model of ARM Versatile Express board
Add a model of the ARM Versatile Express board (with A9MPx4 daughterboard).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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