1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "sysbus.h" 25 #include "arm-misc.h" 26 #include "primecell.h" 27 #include "devices.h" 28 #include "net.h" 29 #include "sysemu.h" 30 #include "boards.h" 31 #include "exec-memory.h" 32 33 #define VEXPRESS_BOARD_ID 0x8e0 34 35 static struct arm_boot_info vexpress_binfo; 36 37 /* Address maps for peripherals: 38 * the Versatile Express motherboard has two possible maps, 39 * the "legacy" one (used for A9) and the "Cortex-A Series" 40 * map (used for newer cores). 41 * Individual daughterboards can also have different maps for 42 * their peripherals. 43 */ 44 45 enum { 46 VE_SYSREGS, 47 VE_SP810, 48 VE_SERIALPCI, 49 VE_PL041, 50 VE_MMCI, 51 VE_KMI0, 52 VE_KMI1, 53 VE_UART0, 54 VE_UART1, 55 VE_UART2, 56 VE_UART3, 57 VE_WDT, 58 VE_TIMER01, 59 VE_TIMER23, 60 VE_SERIALDVI, 61 VE_RTC, 62 VE_COMPACTFLASH, 63 VE_CLCD, 64 VE_NORFLASH0, 65 VE_NORFLASH0ALIAS, 66 VE_NORFLASH1, 67 VE_SRAM, 68 VE_VIDEORAM, 69 VE_ETHERNET, 70 VE_USB, 71 VE_DAPROM, 72 }; 73 74 static target_phys_addr_t motherboard_legacy_map[] = { 75 /* CS7: 0x10000000 .. 0x10020000 */ 76 [VE_SYSREGS] = 0x10000000, 77 [VE_SP810] = 0x10001000, 78 [VE_SERIALPCI] = 0x10002000, 79 [VE_PL041] = 0x10004000, 80 [VE_MMCI] = 0x10005000, 81 [VE_KMI0] = 0x10006000, 82 [VE_KMI1] = 0x10007000, 83 [VE_UART0] = 0x10009000, 84 [VE_UART1] = 0x1000a000, 85 [VE_UART2] = 0x1000b000, 86 [VE_UART3] = 0x1000c000, 87 [VE_WDT] = 0x1000f000, 88 [VE_TIMER01] = 0x10011000, 89 [VE_TIMER23] = 0x10012000, 90 [VE_SERIALDVI] = 0x10016000, 91 [VE_RTC] = 0x10017000, 92 [VE_COMPACTFLASH] = 0x1001a000, 93 [VE_CLCD] = 0x1001f000, 94 /* CS0: 0x40000000 .. 0x44000000 */ 95 [VE_NORFLASH0] = 0x40000000, 96 /* CS1: 0x44000000 .. 0x48000000 */ 97 [VE_NORFLASH1] = 0x44000000, 98 /* CS2: 0x48000000 .. 0x4a000000 */ 99 [VE_SRAM] = 0x48000000, 100 /* CS3: 0x4c000000 .. 0x50000000 */ 101 [VE_VIDEORAM] = 0x4c000000, 102 [VE_ETHERNET] = 0x4e000000, 103 [VE_USB] = 0x4f000000, 104 }; 105 106 /* Structure defining the peculiarities of a specific daughterboard */ 107 108 typedef struct VEDBoardInfo VEDBoardInfo; 109 110 typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, 111 ram_addr_t ram_size, 112 const char *cpu_model, 113 qemu_irq *pic, uint32_t *proc_id); 114 115 struct VEDBoardInfo { 116 const target_phys_addr_t *motherboard_map; 117 target_phys_addr_t loader_start; 118 DBoardInitFn *init; 119 }; 120 121 static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, 122 ram_addr_t ram_size, 123 const char *cpu_model, 124 qemu_irq *pic, uint32_t *proc_id) 125 { 126 CPUState *env = NULL; 127 MemoryRegion *sysmem = get_system_memory(); 128 MemoryRegion *ram = g_new(MemoryRegion, 1); 129 MemoryRegion *lowram = g_new(MemoryRegion, 1); 130 DeviceState *dev; 131 SysBusDevice *busdev; 132 qemu_irq *irqp; 133 int n; 134 qemu_irq cpu_irq[4]; 135 ram_addr_t low_ram_size; 136 137 if (!cpu_model) { 138 cpu_model = "cortex-a9"; 139 } 140 141 *proc_id = 0x0c000191; 142 143 for (n = 0; n < smp_cpus; n++) { 144 env = cpu_init(cpu_model); 145 if (!env) { 146 fprintf(stderr, "Unable to find CPU definition\n"); 147 exit(1); 148 } 149 irqp = arm_pic_init_cpu(env); 150 cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; 151 } 152 153 if (ram_size > 0x40000000) { 154 /* 1GB is the maximum the address space permits */ 155 fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); 156 exit(1); 157 } 158 159 memory_region_init_ram(ram, "vexpress.highmem", ram_size); 160 vmstate_register_ram_global(ram); 161 low_ram_size = ram_size; 162 if (low_ram_size > 0x4000000) { 163 low_ram_size = 0x4000000; 164 } 165 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 166 * address space should in theory be remappable to various 167 * things including ROM or RAM; we always map the RAM there. 168 */ 169 memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size); 170 memory_region_add_subregion(sysmem, 0x0, lowram); 171 memory_region_add_subregion(sysmem, 0x60000000, ram); 172 173 /* 0x1e000000 A9MPCore (SCU) private memory region */ 174 dev = qdev_create(NULL, "a9mpcore_priv"); 175 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 176 qdev_init_nofail(dev); 177 busdev = sysbus_from_qdev(dev); 178 vexpress_binfo.smp_priv_base = 0x1e000000; 179 sysbus_mmio_map(busdev, 0, vexpress_binfo.smp_priv_base); 180 for (n = 0; n < smp_cpus; n++) { 181 sysbus_connect_irq(busdev, n, cpu_irq[n]); 182 } 183 /* Interrupts [42:0] are from the motherboard; 184 * [47:43] are reserved; [63:48] are daughterboard 185 * peripherals. Note that some documentation numbers 186 * external interrupts starting from 32 (because the 187 * A9MP has internal interrupts 0..31). 188 */ 189 for (n = 0; n < 64; n++) { 190 pic[n] = qdev_get_gpio_in(dev, n); 191 } 192 193 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 194 195 /* 0x10020000 PL111 CLCD (daughterboard) */ 196 sysbus_create_simple("pl111", 0x10020000, pic[44]); 197 198 /* 0x10060000 AXI RAM */ 199 /* 0x100e0000 PL341 Dynamic Memory Controller */ 200 /* 0x100e1000 PL354 Static Memory Controller */ 201 /* 0x100e2000 System Configuration Controller */ 202 203 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 204 /* 0x100e5000 SP805 Watchdog module */ 205 /* 0x100e6000 BP147 TrustZone Protection Controller */ 206 /* 0x100e9000 PL301 'Fast' AXI matrix */ 207 /* 0x100ea000 PL301 'Slow' AXI matrix */ 208 /* 0x100ec000 TrustZone Address Space Controller */ 209 /* 0x10200000 CoreSight debug APB */ 210 /* 0x1e00a000 PL310 L2 Cache Controller */ 211 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 212 } 213 214 static const VEDBoardInfo a9_daughterboard = { 215 .motherboard_map = motherboard_legacy_map, 216 .loader_start = 0x60000000, 217 .init = a9_daughterboard_init, 218 }; 219 220 static void vexpress_common_init(const VEDBoardInfo *daughterboard, 221 ram_addr_t ram_size, 222 const char *boot_device, 223 const char *kernel_filename, 224 const char *kernel_cmdline, 225 const char *initrd_filename, 226 const char *cpu_model) 227 { 228 DeviceState *dev, *sysctl, *pl041; 229 qemu_irq pic[64]; 230 uint32_t proc_id; 231 uint32_t sys_id; 232 ram_addr_t vram_size, sram_size; 233 MemoryRegion *sysmem = get_system_memory(); 234 MemoryRegion *vram = g_new(MemoryRegion, 1); 235 MemoryRegion *sram = g_new(MemoryRegion, 1); 236 const target_phys_addr_t *map = daughterboard->motherboard_map; 237 238 daughterboard->init(daughterboard, ram_size, cpu_model, pic, &proc_id); 239 240 /* Motherboard peripherals: the wiring is the same but the 241 * addresses vary between the legacy and A-Series memory maps. 242 */ 243 244 sys_id = 0x1190f500; 245 246 sysctl = qdev_create(NULL, "realview_sysctl"); 247 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 248 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 249 qdev_init_nofail(sysctl); 250 sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, map[VE_SYSREGS]); 251 252 /* VE_SP810: not modelled */ 253 /* VE_SERIALPCI: not modelled */ 254 255 pl041 = qdev_create(NULL, "pl041"); 256 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 257 qdev_init_nofail(pl041); 258 sysbus_mmio_map(sysbus_from_qdev(pl041), 0, map[VE_PL041]); 259 sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[11]); 260 261 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 262 /* Wire up MMC card detect and read-only signals */ 263 qdev_connect_gpio_out(dev, 0, 264 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 265 qdev_connect_gpio_out(dev, 1, 266 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 267 268 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 269 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 270 271 sysbus_create_simple("pl011", map[VE_UART0], pic[5]); 272 sysbus_create_simple("pl011", map[VE_UART1], pic[6]); 273 sysbus_create_simple("pl011", map[VE_UART2], pic[7]); 274 sysbus_create_simple("pl011", map[VE_UART3], pic[8]); 275 276 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 277 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 278 279 /* VE_SERIALDVI: not modelled */ 280 281 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 282 283 /* VE_COMPACTFLASH: not modelled */ 284 285 /* VE_CLCD: not modelled (we use the daughterboard CLCD only) */ 286 287 /* VE_NORFLASH0: not modelled */ 288 /* VE_NORFLASH0ALIAS: not modelled */ 289 /* VE_NORFLASH1: not modelled */ 290 291 sram_size = 0x2000000; 292 memory_region_init_ram(sram, "vexpress.sram", sram_size); 293 vmstate_register_ram_global(sram); 294 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 295 296 vram_size = 0x800000; 297 memory_region_init_ram(vram, "vexpress.vram", vram_size); 298 vmstate_register_ram_global(vram); 299 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 300 301 /* 0x4e000000 LAN9118 Ethernet */ 302 if (nd_table[0].vlan) { 303 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 304 } 305 306 /* VE_USB: not modelled */ 307 308 /* VE_DAPROM: not modelled */ 309 310 vexpress_binfo.ram_size = ram_size; 311 vexpress_binfo.kernel_filename = kernel_filename; 312 vexpress_binfo.kernel_cmdline = kernel_cmdline; 313 vexpress_binfo.initrd_filename = initrd_filename; 314 vexpress_binfo.nb_cpus = smp_cpus; 315 vexpress_binfo.board_id = VEXPRESS_BOARD_ID; 316 vexpress_binfo.loader_start = daughterboard->loader_start; 317 vexpress_binfo.smp_loader_start = map[VE_SRAM]; 318 vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 319 arm_load_kernel(first_cpu, &vexpress_binfo); 320 } 321 322 static void vexpress_a9_init(ram_addr_t ram_size, 323 const char *boot_device, 324 const char *kernel_filename, 325 const char *kernel_cmdline, 326 const char *initrd_filename, 327 const char *cpu_model) 328 { 329 vexpress_common_init(&a9_daughterboard, 330 ram_size, boot_device, kernel_filename, 331 kernel_cmdline, initrd_filename, cpu_model); 332 } 333 334 static QEMUMachine vexpress_a9_machine = { 335 .name = "vexpress-a9", 336 .desc = "ARM Versatile Express for Cortex-A9", 337 .init = vexpress_a9_init, 338 .use_scsi = 1, 339 .max_cpus = 4, 340 }; 341 342 static void vexpress_machine_init(void) 343 { 344 qemu_register_machine(&vexpress_a9_machine); 345 } 346 347 machine_init(vexpress_machine_init); 348