1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "sysbus.h" 25 #include "arm-misc.h" 26 #include "primecell.h" 27 #include "devices.h" 28 #include "net.h" 29 #include "sysemu.h" 30 #include "boards.h" 31 #include "exec-memory.h" 32 33 #define SMP_BOOT_ADDR 0xe0000000 34 35 #define VEXPRESS_BOARD_ID 0x8e0 36 37 static struct arm_boot_info vexpress_binfo = { 38 .smp_loader_start = SMP_BOOT_ADDR, 39 }; 40 41 /* Address maps for peripherals: 42 * the Versatile Express motherboard has two possible maps, 43 * the "legacy" one (used for A9) and the "Cortex-A Series" 44 * map (used for newer cores). 45 * Individual daughterboards can also have different maps for 46 * their peripherals. 47 */ 48 49 enum { 50 VE_SYSREGS, 51 VE_SP810, 52 VE_SERIALPCI, 53 VE_PL041, 54 VE_MMCI, 55 VE_KMI0, 56 VE_KMI1, 57 VE_UART0, 58 VE_UART1, 59 VE_UART2, 60 VE_UART3, 61 VE_WDT, 62 VE_TIMER01, 63 VE_TIMER23, 64 VE_SERIALDVI, 65 VE_RTC, 66 VE_COMPACTFLASH, 67 VE_CLCD, 68 VE_NORFLASH0, 69 VE_NORFLASH0ALIAS, 70 VE_NORFLASH1, 71 VE_SRAM, 72 VE_VIDEORAM, 73 VE_ETHERNET, 74 VE_USB, 75 VE_DAPROM, 76 }; 77 78 static target_phys_addr_t motherboard_legacy_map[] = { 79 /* CS7: 0x10000000 .. 0x10020000 */ 80 [VE_SYSREGS] = 0x10000000, 81 [VE_SP810] = 0x10001000, 82 [VE_SERIALPCI] = 0x10002000, 83 [VE_PL041] = 0x10004000, 84 [VE_MMCI] = 0x10005000, 85 [VE_KMI0] = 0x10006000, 86 [VE_KMI1] = 0x10007000, 87 [VE_UART0] = 0x10009000, 88 [VE_UART1] = 0x1000a000, 89 [VE_UART2] = 0x1000b000, 90 [VE_UART3] = 0x1000c000, 91 [VE_WDT] = 0x1000f000, 92 [VE_TIMER01] = 0x10011000, 93 [VE_TIMER23] = 0x10012000, 94 [VE_SERIALDVI] = 0x10016000, 95 [VE_RTC] = 0x10017000, 96 [VE_COMPACTFLASH] = 0x1001a000, 97 [VE_CLCD] = 0x1001f000, 98 /* CS0: 0x40000000 .. 0x44000000 */ 99 [VE_NORFLASH0] = 0x40000000, 100 /* CS1: 0x44000000 .. 0x48000000 */ 101 [VE_NORFLASH1] = 0x44000000, 102 /* CS2: 0x48000000 .. 0x4a000000 */ 103 [VE_SRAM] = 0x48000000, 104 /* CS3: 0x4c000000 .. 0x50000000 */ 105 [VE_VIDEORAM] = 0x4c000000, 106 [VE_ETHERNET] = 0x4e000000, 107 [VE_USB] = 0x4f000000, 108 }; 109 110 static void vexpress_a9_init(ram_addr_t ram_size, 111 const char *boot_device, 112 const char *kernel_filename, const char *kernel_cmdline, 113 const char *initrd_filename, const char *cpu_model) 114 { 115 CPUState *env = NULL; 116 MemoryRegion *sysmem = get_system_memory(); 117 MemoryRegion *ram = g_new(MemoryRegion, 1); 118 MemoryRegion *lowram = g_new(MemoryRegion, 1); 119 MemoryRegion *vram = g_new(MemoryRegion, 1); 120 MemoryRegion *sram = g_new(MemoryRegion, 1); 121 MemoryRegion *hackram = g_new(MemoryRegion, 1); 122 DeviceState *dev, *sysctl, *pl041; 123 SysBusDevice *busdev; 124 qemu_irq *irqp; 125 qemu_irq pic[64]; 126 int n; 127 qemu_irq cpu_irq[4]; 128 uint32_t proc_id; 129 uint32_t sys_id; 130 ram_addr_t low_ram_size, vram_size, sram_size; 131 target_phys_addr_t *map = motherboard_legacy_map; 132 133 if (!cpu_model) { 134 cpu_model = "cortex-a9"; 135 } 136 137 for (n = 0; n < smp_cpus; n++) { 138 env = cpu_init(cpu_model); 139 if (!env) { 140 fprintf(stderr, "Unable to find CPU definition\n"); 141 exit(1); 142 } 143 irqp = arm_pic_init_cpu(env); 144 cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; 145 } 146 147 if (ram_size > 0x40000000) { 148 /* 1GB is the maximum the address space permits */ 149 fprintf(stderr, "vexpress: cannot model more than 1GB RAM\n"); 150 exit(1); 151 } 152 153 memory_region_init_ram(ram, "vexpress.highmem", ram_size); 154 vmstate_register_ram_global(ram); 155 low_ram_size = ram_size; 156 if (low_ram_size > 0x4000000) { 157 low_ram_size = 0x4000000; 158 } 159 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 160 * address space should in theory be remappable to various 161 * things including ROM or RAM; we always map the RAM there. 162 */ 163 memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size); 164 memory_region_add_subregion(sysmem, 0x0, lowram); 165 memory_region_add_subregion(sysmem, 0x60000000, ram); 166 167 /* 0x1e000000 A9MPCore (SCU) private memory region */ 168 dev = qdev_create(NULL, "a9mpcore_priv"); 169 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 170 qdev_init_nofail(dev); 171 busdev = sysbus_from_qdev(dev); 172 vexpress_binfo.smp_priv_base = 0x1e000000; 173 sysbus_mmio_map(busdev, 0, vexpress_binfo.smp_priv_base); 174 for (n = 0; n < smp_cpus; n++) { 175 sysbus_connect_irq(busdev, n, cpu_irq[n]); 176 } 177 /* Interrupts [42:0] are from the motherboard; 178 * [47:43] are reserved; [63:48] are daughterboard 179 * peripherals. Note that some documentation numbers 180 * external interrupts starting from 32 (because the 181 * A9MP has internal interrupts 0..31). 182 */ 183 for (n = 0; n < 64; n++) { 184 pic[n] = qdev_get_gpio_in(dev, n); 185 } 186 187 /* Motherboard peripherals: the wiring is the same but the 188 * addresses vary between the legacy and A-Series memory maps. 189 */ 190 191 sys_id = 0x1190f500; 192 proc_id = 0x0c000191; 193 194 sysctl = qdev_create(NULL, "realview_sysctl"); 195 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 196 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 197 qdev_init_nofail(sysctl); 198 sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, map[VE_SYSREGS]); 199 200 /* VE_SP810: not modelled */ 201 /* VE_SERIALPCI: not modelled */ 202 203 pl041 = qdev_create(NULL, "pl041"); 204 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 205 qdev_init_nofail(pl041); 206 sysbus_mmio_map(sysbus_from_qdev(pl041), 0, map[VE_PL041]); 207 sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[11]); 208 209 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 210 /* Wire up MMC card detect and read-only signals */ 211 qdev_connect_gpio_out(dev, 0, 212 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 213 qdev_connect_gpio_out(dev, 1, 214 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 215 216 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 217 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 218 219 sysbus_create_simple("pl011", map[VE_UART0], pic[5]); 220 sysbus_create_simple("pl011", map[VE_UART1], pic[6]); 221 sysbus_create_simple("pl011", map[VE_UART2], pic[7]); 222 sysbus_create_simple("pl011", map[VE_UART3], pic[8]); 223 224 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 225 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 226 227 /* VE_SERIALDVI: not modelled */ 228 229 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 230 231 /* VE_COMPACTFLASH: not modelled */ 232 233 /* VE_CLCD: not modelled (we use the daughterboard CLCD only) */ 234 235 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 236 237 /* 0x10020000 PL111 CLCD (daughterboard) */ 238 sysbus_create_simple("pl111", 0x10020000, pic[44]); 239 240 /* 0x10060000 AXI RAM */ 241 /* 0x100e0000 PL341 Dynamic Memory Controller */ 242 /* 0x100e1000 PL354 Static Memory Controller */ 243 /* 0x100e2000 System Configuration Controller */ 244 245 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 246 /* 0x100e5000 SP805 Watchdog module */ 247 /* 0x100e6000 BP147 TrustZone Protection Controller */ 248 /* 0x100e9000 PL301 'Fast' AXI matrix */ 249 /* 0x100ea000 PL301 'Slow' AXI matrix */ 250 /* 0x100ec000 TrustZone Address Space Controller */ 251 /* 0x10200000 CoreSight debug APB */ 252 /* 0x1e00a000 PL310 L2 Cache Controller */ 253 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 254 255 /* VE_NORFLASH0: not modelled */ 256 /* VE_NORFLASH0ALIAS: not modelled */ 257 /* VE_NORFLASH1: not modelled */ 258 259 sram_size = 0x2000000; 260 memory_region_init_ram(sram, "vexpress.sram", sram_size); 261 vmstate_register_ram_global(sram); 262 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 263 264 vram_size = 0x800000; 265 memory_region_init_ram(vram, "vexpress.vram", vram_size); 266 vmstate_register_ram_global(vram); 267 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 268 269 /* 0x4e000000 LAN9118 Ethernet */ 270 if (nd_table[0].vlan) { 271 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 272 } 273 274 /* VE_USB: not modelled */ 275 276 /* VE_DAPROM: not modelled */ 277 278 /* ??? Hack to map an additional page of ram for the secondary CPU 279 startup code. I guess this works on real hardware because the 280 BootROM happens to be in ROM/flash or in memory that isn't clobbered 281 until after Linux boots the secondary CPUs. */ 282 memory_region_init_ram(hackram, "vexpress.hack", 0x1000); 283 vmstate_register_ram_global(hackram); 284 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, hackram); 285 286 vexpress_binfo.ram_size = ram_size; 287 vexpress_binfo.kernel_filename = kernel_filename; 288 vexpress_binfo.kernel_cmdline = kernel_cmdline; 289 vexpress_binfo.initrd_filename = initrd_filename; 290 vexpress_binfo.nb_cpus = smp_cpus; 291 vexpress_binfo.board_id = VEXPRESS_BOARD_ID; 292 vexpress_binfo.loader_start = 0x60000000; 293 vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 294 arm_load_kernel(first_cpu, &vexpress_binfo); 295 } 296 297 298 static QEMUMachine vexpress_a9_machine = { 299 .name = "vexpress-a9", 300 .desc = "ARM Versatile Express for Cortex-A9", 301 .init = vexpress_a9_init, 302 .use_scsi = 1, 303 .max_cpus = 4, 304 }; 305 306 static void vexpress_machine_init(void) 307 { 308 qemu_register_machine(&vexpress_a9_machine); 309 } 310 311 machine_init(vexpress_machine_init); 312