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0cc3a351 |
| 22-Feb-2025 |
Sean Christopherson <seanjc@google.com> |
lib: Use __ASSEMBLER__ instead of __ASSEMBLY__
Convert all non-x86 #ifdefs from __ASSEMBLY__ to __ASSEMBLER__, and remove all manual __ASSEMBLY__ #defines. __ASSEMBLY_ was inherited blindly from th
lib: Use __ASSEMBLER__ instead of __ASSEMBLY__
Convert all non-x86 #ifdefs from __ASSEMBLY__ to __ASSEMBLER__, and remove all manual __ASSEMBLY__ #defines. __ASSEMBLY_ was inherited blindly from the Linux kernel, and must be manually defined, e.g. through build rules or with the aforementioned explicit #defines in assembly code.
__ASSEMBLER__ on the other hand is automatically defined by the compiler when preprocessing assembly, i.e. doesn't require manually #defines for the code to function correctly.
Ignore x86, as x86 doesn't actually rely on __ASSEMBLY__ at the moment, and is undergoing a parallel cleanup.
Signed-off-by: Sean Christopherson <seanjc@google.com> Reviewed-by: Andrew Jones <andrew.jones@linux.dev> Message-ID: <20250222014526.2302653-1-seanjc@google.com> [thuth: Fix three more occurances in libfdt.h and sbi-tests.h] Signed-off-by: Thomas Huth <thuth@redhat.com>
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48d59524 |
| 02-Feb-2024 |
Andrew Jones <andrew.jones@linux.dev> |
Merge branch 'riscv/initial-port-v3' into 'master'
riscv: Initial port
See merge request kvm-unit-tests/kvm-unit-tests!50
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dfc1fec2 |
| 24-Sep-2023 |
Andrew Jones <andrew.jones@linux.dev> |
arm/arm64: Move cpumask.h to common lib
RISC-V will also make use of cpumask.h, so move it to the arch-common directory.
Signed-off-by: Andrew Jones <andrew.jones@linux.dev> Reviewed-by: Thomas Hut
arm/arm64: Move cpumask.h to common lib
RISC-V will also make use of cpumask.h, so move it to the arch-common directory.
Signed-off-by: Andrew Jones <andrew.jones@linux.dev> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com>
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9c537510 |
| 31-Jul-2020 |
Jingyi Wang <wangjingyi11@huawei.com> |
arm64: microbench: gic: Add ipi latency test for gicv4.1 support kvm
If gicv4.1(sgi hardware injection) is supported in kvm, we test ipi injection via hw/sw way separately.
Signed-off-by: Jingyi Wa
arm64: microbench: gic: Add ipi latency test for gicv4.1 support kvm
If gicv4.1(sgi hardware injection) is supported in kvm, we test ipi injection via hw/sw way separately.
Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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7af37ec6 |
| 31-Jul-2020 |
Jingyi Wang <wangjingyi11@huawei.com> |
arm64: microbench: gic: Add ipi latency test for gicv4.1 support kvm
If gicv4.1(sgi hardware injection) is supported in kvm, we test ipi injection via hw/sw way separately.
Signed-off-by: Jingyi Wa
arm64: microbench: gic: Add ipi latency test for gicv4.1 support kvm
If gicv4.1(sgi hardware injection) is supported in kvm, we test ipi injection via hw/sw way separately.
Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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80374e12 |
| 02-Apr-2020 |
Eric Auger <eric.auger@redhat.com> |
arm/arm64: ITS: its_enable_defaults
its_enable_defaults() enable LPIs at redistributor level and ITS level.
gicv3_enable_defaults must be called before.
Signed-off-by: Eric Auger <eric.auger@redha
arm/arm64: ITS: its_enable_defaults
its_enable_defaults() enable LPIs at redistributor level and ITS level.
gicv3_enable_defaults must be called before.
Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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05d1bb91 |
| 02-Apr-2020 |
Eric Auger <eric.auger@redhat.com> |
arm/arm64: gicv3: Set the LPI config and pending tables
Allocate the LPI configuration and per re-distributor pending table. Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled by defa
arm/arm64: gicv3: Set the LPI config and pending tables
Allocate the LPI configuration and per re-distributor pending table. Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled by default in the config table.
Also introduce a helper routine that allows to set the pending table bit for a given LPI and macros to set/get its configuration.
Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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d24709d3 |
| 02-Apr-2020 |
Eric Auger <eric.auger@redhat.com> |
arm/arm64: gicv3: Add some re-distributor defines
PROPBASER, PENDBASE and GICR_CTRL will be used for LPI management.
Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Zenghui Yu <yuzen
arm/arm64: gicv3: Add some re-distributor defines
PROPBASER, PENDBASE and GICR_CTRL will be used for LPI management.
Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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401c09ea |
| 11-Feb-2020 |
Zenghui Yu <yuzenghui@huawei.com> |
arm64: timer: Use the proper RDist register name in GICv3
We're actually going to read GICR_ISACTIVER0 and GICR_ISPENDR0 (in SGI_base frame of the redistribitor) to get the active/pending state of t
arm64: timer: Use the proper RDist register name in GICv3
We're actually going to read GICR_ISACTIVER0 and GICR_ISPENDR0 (in SGI_base frame of the redistribitor) to get the active/pending state of the timer interrupt. Fix this typo.
And since they have the same value, there's no functional change.
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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3c13c642 |
| 08-Jan-2020 |
Paolo Bonzini <pbonzini@redhat.com> |
Merge branch 'arm/queue' of https://github.com/rhdrjones/kvm-unit-tests into HEAD
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08ae0906 |
| 31-Dec-2019 |
Alexandru Elisei <alexandru.elisei@arm.com> |
arm64: timer: Write to ICENABLER to disable timer IRQ
According the Generic Interrupt Controller versions 2, 3 and 4 architecture specifications, a write of 0 to the GIC{D,R}_ISENABLER{,0} registers
arm64: timer: Write to ICENABLER to disable timer IRQ
According the Generic Interrupt Controller versions 2, 3 and 4 architecture specifications, a write of 0 to the GIC{D,R}_ISENABLER{,0} registers is ignored; this is also how KVM emulates the corresponding register. Write instead to the ICENABLER register when disabling the timer interrupt.
Note that fortunately for us, the timer test was still working as intended because KVM does the sensible thing and all interrupts are disabled by default when creating a VM.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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a5a2d35c |
| 05-Sep-2018 |
Andrew Jones <drjones@redhat.com> |
arm/arm64: gicv3: support up to 8 redistributor regions
We need to support at least two redistributor regions in order to support more than 123 vcpus (we select 8 because that should be plenty). Als
arm/arm64: gicv3: support up to 8 redistributor regions
We need to support at least two redistributor regions in order to support more than 123 vcpus (we select 8 because that should be plenty). Also bump NR_CPUS to 512, since that's what KVM currently supports.
Signed-off-by: Andrew Jones <drjones@redhat.com> Tested-by: Christoffer Dall <christoffer.dall@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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ea325c68 |
| 22-Dec-2016 |
Paolo Bonzini <pbonzini@redhat.com> |
Merge tag 'for-master' of https://github.com/rhdrjones/kvm-unit-tests into HEAD
arm/arm64 patches ready for master
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2e2d471d |
| 13-May-2016 |
Andrew Jones <drjones@redhat.com> |
arm/arm64: gicv3: add an IPI test
Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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91a6c3ce |
| 08-Nov-2016 |
Andrew Jones <drjones@redhat.com> |
arm/arm64: add initial gicv3 support
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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