1 /* 2 * All GIC* defines are lifted from include/linux/irqchip/arm-gic-v3.h 3 * 4 * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 #ifndef _ASMARM_GIC_V3_H_ 9 #define _ASMARM_GIC_V3_H_ 10 11 #ifndef _ASMARM_GIC_H_ 12 #error Do not directly include <asm/gic-v3.h>. Include <asm/gic.h> 13 #endif 14 15 /* 16 * Distributor registers 17 * 18 * We expect to be run in Non-secure mode, thus we define the 19 * group1 enable bits with respect to that view. 20 */ 21 #define GICD_CTLR 0x0000 22 #define GICD_CTLR_RWP (1U << 31) 23 #define GICD_CTLR_ARE_NS (1U << 4) 24 #define GICD_CTLR_ENABLE_G1A (1U << 1) 25 #define GICD_CTLR_ENABLE_G1 (1U << 0) 26 27 /* Re-Distributor registers, offsets from RD_base */ 28 #define GICR_TYPER 0x0008 29 30 #define GICR_TYPER_LAST (1U << 4) 31 32 /* Re-Distributor registers, offsets from SGI_base */ 33 #define GICR_IGROUPR0 GICD_IGROUPR 34 #define GICR_ISENABLER0 GICD_ISENABLER 35 #define GICR_ICENABLER0 GICD_ICENABLER 36 #define GICR_ISPENDR0 GICD_ISPENDR 37 #define GICR_ICPENDR0 GICD_ICPENDR 38 #define GICR_ISACTIVER0 GICD_ISACTIVER 39 #define GICR_ICACTIVER0 GICD_ICACTIVER 40 #define GICR_IPRIORITYR0 GICD_IPRIORITYR 41 42 #define GICR_PROPBASER 0x0070 43 #define GICR_PENDBASER 0x0078 44 #define GICR_CTLR GICD_CTLR 45 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) 46 47 #define ICC_SGI1R_AFFINITY_1_SHIFT 16 48 #define ICC_SGI1R_AFFINITY_2_SHIFT 32 49 #define ICC_SGI1R_AFFINITY_3_SHIFT 48 50 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 51 (MPIDR_AFFINITY_LEVEL(cluster_id, level) << ICC_SGI1R_AFFINITY_## level ## _SHIFT) 52 53 #include <asm/arch_gicv3.h> 54 55 #ifndef __ASSEMBLY__ 56 #include <asm/setup.h> 57 #include <asm/processor.h> 58 #include <asm/delay.h> 59 #include <asm/cpumask.h> 60 #include <asm/smp.h> 61 #include <asm/io.h> 62 63 #define GICV3_NR_REDISTS 8 64 65 struct gicv3_data { 66 void *dist_base; 67 void *redist_bases[GICV3_NR_REDISTS]; 68 void *redist_base[NR_CPUS]; 69 unsigned int irq_nr; 70 }; 71 extern struct gicv3_data gicv3_data; 72 73 #define gicv3_dist_base() (gicv3_data.dist_base) 74 #define gicv3_redist_base() (gicv3_data.redist_base[smp_processor_id()]) 75 #define gicv3_sgi_base() (gicv3_data.redist_base[smp_processor_id()] + SZ_64K) 76 77 extern int gicv3_init(void); 78 extern void gicv3_enable_defaults(void); 79 extern u32 gicv3_read_iar(void); 80 extern u32 gicv3_iar_irqnr(u32 iar); 81 extern void gicv3_write_eoir(u32 irqstat); 82 extern void gicv3_ipi_send_single(int irq, int cpu); 83 extern void gicv3_ipi_send_mask(int irq, const cpumask_t *dest); 84 extern void gicv3_set_redist_base(size_t stride); 85 86 static inline void gicv3_do_wait_for_rwp(void *base) 87 { 88 int count = 100000; /* 1s */ 89 90 while (readl(base + GICD_CTLR) & GICD_CTLR_RWP) { 91 if (!--count) { 92 printf("GICv3: RWP timeout!\n"); 93 abort(); 94 } 95 cpu_relax(); 96 udelay(10); 97 }; 98 } 99 100 static inline void gicv3_dist_wait_for_rwp(void) 101 { 102 gicv3_do_wait_for_rwp(gicv3_dist_base()); 103 } 104 105 static inline void gicv3_redist_wait_for_uwp(void) 106 { 107 /* 108 * We can build on gic_do_wait_for_rwp, which uses GICD_ registers 109 * because GICD_CTLR == GICR_CTLR and GICD_CTLR_RWP == GICR_CTLR_UWP 110 */ 111 gicv3_do_wait_for_rwp(gicv3_redist_base()); 112 } 113 114 static inline u32 mpidr_compress(u64 mpidr) 115 { 116 u64 compressed = mpidr & MPIDR_HWID_BITMASK; 117 118 compressed = (((compressed >> 32) & 0xff) << 24) | compressed; 119 return compressed; 120 } 121 122 static inline u64 mpidr_uncompress(u32 compressed) 123 { 124 u64 mpidr = ((u64)compressed >> 24) << 32; 125 126 mpidr |= compressed & MPIDR_HWID_BITMASK; 127 return mpidr; 128 } 129 130 #endif /* !__ASSEMBLY__ */ 131 #endif /* _ASMARM_GIC_V3_H_ */ 132