1 /*-
2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include "opt_inet6.h"
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/condvar.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
37 #include <sys/sbuf.h>
38 #include <sys/socket.h>
39 #include <sys/sysctl.h>
40 #include <sys/unistd.h>
41
42 #include <net/if.h>
43 #include <net/if_var.h>
44 #include <net/if_media.h>
45
46 /* needed for checksum offload */
47 #include <netinet/in.h>
48 #include <netinet/ip.h>
49 #ifdef INET6
50 #include <netinet/ip6.h>
51 #include <netinet6/ip6_var.h>
52 #endif
53
54 #include <dev/mii/mii.h>
55 #include <dev/mii/miivar.h>
56
57 #include <dev/usb/usb.h>
58 #include <dev/usb/usbdi.h>
59 #include <dev/usb/usbdi_util.h>
60 #include "usbdevs.h"
61
62 #define USB_DEBUG_VAR ure_debug
63 #include <dev/usb/usb_debug.h>
64 #include <dev/usb/usb_process.h>
65
66 #include <dev/usb/net/usb_ethernet.h>
67 #include <dev/usb/net/if_urereg.h>
68
69 #include "miibus_if.h"
70
71 #ifdef USB_DEBUG
72 static int ure_debug = 0;
73
74 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
75 "USB ure");
76 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
77 "Debug level");
78 #endif
79
80 #ifdef USB_DEBUG_VAR
81 #ifdef USB_DEBUG
82 #define DEVPRINTFN(n,dev,fmt,...) do { \
83 if ((USB_DEBUG_VAR) >= (n)) { \
84 device_printf((dev), "%s: " fmt, \
85 __FUNCTION__ ,##__VA_ARGS__); \
86 } \
87 } while (0)
88 #define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__)
89 #else
90 #define DEVPRINTF(...) do { } while (0)
91 #define DEVPRINTFN(...) do { } while (0)
92 #endif
93 #endif
94
95 /*
96 * Various supported device vendors/products.
97 */
98 static const STRUCT_USB_HOST_ID ure_devs[] = {
99 #define URE_DEV(v,p,i) { \
100 USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i), \
101 USB_IFACE_CLASS(UICLASS_VENDOR), \
102 USB_IFACE_SUBCLASS(UISUBCLASS_VENDOR) }
103 URE_DEV(ELECOM, EDCQUA3C, 0),
104 URE_DEV(LENOVO, RTL8153, URE_FLAG_8153),
105 URE_DEV(LENOVO, TBT3LANGEN2, 0),
106 URE_DEV(LENOVO, ONELINK, 0),
107 URE_DEV(LENOVO, RTL8153_04, URE_FLAG_8153),
108 URE_DEV(LENOVO, ONELINKPLUS, URE_FLAG_8153),
109 URE_DEV(LENOVO, USBCLAN, 0),
110 URE_DEV(LENOVO, USBCLANGEN2, 0),
111 URE_DEV(LENOVO, USBCLANHYBRID, 0),
112 URE_DEV(MICROSOFT, WINDEVETH, 0),
113 URE_DEV(NVIDIA, RTL8153, URE_FLAG_8153),
114 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
115 URE_DEV(REALTEK, RTL8153, URE_FLAG_8153),
116 URE_DEV(TPLINK, RTL8153, URE_FLAG_8153),
117 URE_DEV(REALTEK, RTL8156, URE_FLAG_8156),
118 #undef URE_DEV
119 };
120
121 static device_probe_t ure_probe;
122 static device_attach_t ure_attach;
123 static device_detach_t ure_detach;
124
125 static usb_callback_t ure_bulk_read_callback;
126 static usb_callback_t ure_bulk_write_callback;
127
128 static miibus_readreg_t ure_miibus_readreg;
129 static miibus_writereg_t ure_miibus_writereg;
130 static miibus_statchg_t ure_miibus_statchg;
131 static miibus_linkchg_t ure_miibus_linkchg;
132
133 static uether_fn_t ure_attach_post;
134 static uether_fn_t ure_init;
135 static uether_fn_t ure_stop;
136 static uether_fn_t ure_start;
137 static uether_fn_t ure_tick;
138 static uether_fn_t ure_rxfilter;
139
140 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
141 void *, int);
142 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
143 int);
144 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
145 int);
146 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t);
147 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
148 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
149 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
150 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
151 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
152 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
153 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
154 static void ure_sram_write(struct ure_softc *, uint16_t, uint16_t);
155
156 static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS);
157
158 static void ure_read_chipver(struct ure_softc *);
159 static int ure_attach_post_sub(struct usb_ether *);
160 static void ure_reset(struct ure_softc *);
161 static int ure_ifmedia_upd(if_t);
162 static void ure_ifmedia_sts(if_t, struct ifmediareq *);
163 static void ure_add_media_types(struct ure_softc *);
164 static void ure_link_state(struct ure_softc *sc);
165 static int ure_get_link_status(struct ure_softc *);
166 static int ure_ioctl(if_t, u_long, caddr_t);
167 static void ure_rtl8152_init(struct ure_softc *);
168 static void ure_rtl8152_nic_reset(struct ure_softc *);
169 static void ure_rtl8153_init(struct ure_softc *);
170 static void ure_rtl8153b_init(struct ure_softc *);
171 static void ure_rtl8153b_nic_reset(struct ure_softc *);
172 static void ure_disable_teredo(struct ure_softc *);
173 static void ure_enable_aldps(struct ure_softc *, bool);
174 static uint16_t ure_phy_status(struct ure_softc *, uint16_t);
175 static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m);
176 static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout);
177
178 static device_method_t ure_methods[] = {
179 /* Device interface. */
180 DEVMETHOD(device_probe, ure_probe),
181 DEVMETHOD(device_attach, ure_attach),
182 DEVMETHOD(device_detach, ure_detach),
183
184 /* MII interface. */
185 DEVMETHOD(miibus_readreg, ure_miibus_readreg),
186 DEVMETHOD(miibus_writereg, ure_miibus_writereg),
187 DEVMETHOD(miibus_statchg, ure_miibus_statchg),
188 DEVMETHOD(miibus_linkchg, ure_miibus_linkchg),
189
190 DEVMETHOD_END
191 };
192
193 static driver_t ure_driver = {
194 .name = "ure",
195 .methods = ure_methods,
196 .size = sizeof(struct ure_softc),
197 };
198
199 DRIVER_MODULE(ure, uhub, ure_driver, NULL, NULL);
200 DRIVER_MODULE(miibus, ure, miibus_driver, NULL, NULL);
201 MODULE_DEPEND(ure, uether, 1, 1, 1);
202 MODULE_DEPEND(ure, usb, 1, 1, 1);
203 MODULE_DEPEND(ure, ether, 1, 1, 1);
204 MODULE_DEPEND(ure, miibus, 1, 1, 1);
205 MODULE_VERSION(ure, 1);
206 USB_PNP_HOST_INFO(ure_devs);
207
208 static const struct usb_ether_methods ure_ue_methods = {
209 .ue_attach_post = ure_attach_post,
210 .ue_attach_post_sub = ure_attach_post_sub,
211 .ue_start = ure_start,
212 .ue_init = ure_init,
213 .ue_stop = ure_stop,
214 .ue_tick = ure_tick,
215 .ue_setmulti = ure_rxfilter,
216 .ue_setpromisc = ure_rxfilter,
217 .ue_mii_upd = ure_ifmedia_upd,
218 .ue_mii_sts = ure_ifmedia_sts,
219 };
220
221 #define URE_SETBIT_1(sc, reg, index, x) \
222 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x))
223 #define URE_SETBIT_2(sc, reg, index, x) \
224 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x))
225 #define URE_SETBIT_4(sc, reg, index, x) \
226 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x))
227
228 #define URE_CLRBIT_1(sc, reg, index, x) \
229 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x))
230 #define URE_CLRBIT_2(sc, reg, index, x) \
231 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x))
232 #define URE_CLRBIT_4(sc, reg, index, x) \
233 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x))
234
235 static int
ure_ctl(struct ure_softc * sc,uint8_t rw,uint16_t val,uint16_t index,void * buf,int len)236 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
237 void *buf, int len)
238 {
239 struct usb_device_request req;
240
241 URE_LOCK_ASSERT(sc, MA_OWNED);
242
243 if (rw == URE_CTL_WRITE)
244 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
245 else
246 req.bmRequestType = UT_READ_VENDOR_DEVICE;
247 req.bRequest = UR_SET_ADDRESS;
248 USETW(req.wValue, val);
249 USETW(req.wIndex, index);
250 USETW(req.wLength, len);
251
252 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
253 }
254
255 static int
ure_read_mem(struct ure_softc * sc,uint16_t addr,uint16_t index,void * buf,int len)256 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
257 void *buf, int len)
258 {
259
260 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
261 }
262
263 static int
ure_write_mem(struct ure_softc * sc,uint16_t addr,uint16_t index,void * buf,int len)264 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
265 void *buf, int len)
266 {
267
268 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
269 }
270
271 static uint8_t
ure_read_1(struct ure_softc * sc,uint16_t reg,uint16_t index)272 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
273 {
274 uint32_t val;
275 uint8_t temp[4];
276 uint8_t shift;
277
278 shift = (reg & 3) << 3;
279 reg &= ~3;
280
281 ure_read_mem(sc, reg, index, &temp, 4);
282 val = UGETDW(temp);
283 val >>= shift;
284
285 return (val & 0xff);
286 }
287
288 static uint16_t
ure_read_2(struct ure_softc * sc,uint16_t reg,uint16_t index)289 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
290 {
291 uint32_t val;
292 uint8_t temp[4];
293 uint8_t shift;
294
295 shift = (reg & 2) << 3;
296 reg &= ~3;
297
298 ure_read_mem(sc, reg, index, &temp, 4);
299 val = UGETDW(temp);
300 val >>= shift;
301
302 return (val & 0xffff);
303 }
304
305 static uint32_t
ure_read_4(struct ure_softc * sc,uint16_t reg,uint16_t index)306 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
307 {
308 uint8_t temp[4];
309
310 ure_read_mem(sc, reg, index, &temp, 4);
311 return (UGETDW(temp));
312 }
313
314 static int
ure_write_1(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)315 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
316 {
317 uint16_t byen;
318 uint8_t temp[4];
319 uint8_t shift;
320
321 byen = URE_BYTE_EN_BYTE;
322 shift = reg & 3;
323 val &= 0xff;
324
325 if (reg & 3) {
326 byen <<= shift;
327 val <<= (shift << 3);
328 reg &= ~3;
329 }
330
331 USETDW(temp, val);
332 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
333 }
334
335 static int
ure_write_2(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)336 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
337 {
338 uint16_t byen;
339 uint8_t temp[4];
340 uint8_t shift;
341
342 byen = URE_BYTE_EN_WORD;
343 shift = reg & 2;
344 val &= 0xffff;
345
346 if (reg & 2) {
347 byen <<= shift;
348 val <<= (shift << 3);
349 reg &= ~3;
350 }
351
352 USETDW(temp, val);
353 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
354 }
355
356 static int
ure_write_4(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)357 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
358 {
359 uint8_t temp[4];
360
361 USETDW(temp, val);
362 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
363 }
364
365 static uint16_t
ure_ocp_reg_read(struct ure_softc * sc,uint16_t addr)366 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
367 {
368 uint16_t reg;
369
370 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
371 reg = (addr & 0x0fff) | 0xb000;
372
373 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
374 }
375
376 static void
ure_ocp_reg_write(struct ure_softc * sc,uint16_t addr,uint16_t data)377 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
378 {
379 uint16_t reg;
380
381 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
382 reg = (addr & 0x0fff) | 0xb000;
383
384 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
385 }
386
387 static void
ure_sram_write(struct ure_softc * sc,uint16_t addr,uint16_t data)388 ure_sram_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
389 {
390 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, addr);
391 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, data);
392 }
393
394 static int
ure_miibus_readreg(device_t dev,int phy,int reg)395 ure_miibus_readreg(device_t dev, int phy, int reg)
396 {
397 struct ure_softc *sc;
398 uint16_t val;
399 int locked;
400
401 sc = device_get_softc(dev);
402 locked = mtx_owned(&sc->sc_mtx);
403 if (!locked)
404 URE_LOCK(sc);
405
406 /* Let the rgephy driver read the URE_GMEDIASTAT register. */
407 if (reg == URE_GMEDIASTAT) {
408 if (!locked)
409 URE_UNLOCK(sc);
410 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
411 }
412
413 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
414
415 if (!locked)
416 URE_UNLOCK(sc);
417 return (val);
418 }
419
420 static int
ure_miibus_writereg(device_t dev,int phy,int reg,int val)421 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
422 {
423 struct ure_softc *sc;
424 int locked;
425
426 sc = device_get_softc(dev);
427 if (sc->sc_phyno != phy)
428 return (0);
429
430 locked = mtx_owned(&sc->sc_mtx);
431 if (!locked)
432 URE_LOCK(sc);
433
434 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
435
436 if (!locked)
437 URE_UNLOCK(sc);
438 return (0);
439 }
440
441 static void
ure_miibus_statchg(device_t dev)442 ure_miibus_statchg(device_t dev)
443 {
444 struct ure_softc *sc;
445 struct mii_data *mii;
446 if_t ifp;
447 int locked;
448 uint16_t bmsr;
449 bool new_link, old_link;
450
451 sc = device_get_softc(dev);
452 mii = GET_MII(sc);
453 locked = mtx_owned(&sc->sc_mtx);
454 if (!locked)
455 URE_LOCK(sc);
456
457 ifp = uether_getifp(&sc->sc_ue);
458 if (mii == NULL || ifp == NULL ||
459 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
460 goto done;
461
462 old_link = (sc->sc_flags & URE_FLAG_LINK) ? true : false;
463 sc->sc_flags &= ~URE_FLAG_LINK;
464 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
465 (IFM_ACTIVE | IFM_AVALID)) {
466 switch (IFM_SUBTYPE(mii->mii_media_active)) {
467 case IFM_10_T:
468 case IFM_100_TX:
469 sc->sc_flags |= URE_FLAG_LINK;
470 sc->sc_rxstarted = 0;
471 break;
472 case IFM_1000_T:
473 if ((sc->sc_flags & URE_FLAG_8152) != 0)
474 break;
475 sc->sc_flags |= URE_FLAG_LINK;
476 sc->sc_rxstarted = 0;
477 break;
478 default:
479 break;
480 }
481 }
482
483 new_link = (sc->sc_flags & URE_FLAG_LINK) ? true : false;
484 if (old_link && !new_link) {
485 /*
486 * MII layer reports link down. Verify by reading
487 * the PHY BMSR register directly. BMSR link status
488 * is latched-low, so read twice: first clears any
489 * stale latch, second gives current state.
490 */
491 (void)ure_ocp_reg_read(sc,
492 URE_OCP_BASE_MII + MII_BMSR * 2);
493 bmsr = ure_ocp_reg_read(sc,
494 URE_OCP_BASE_MII + MII_BMSR * 2);
495
496 if (bmsr & BMSR_LINK) {
497 /*
498 * PHY still has link. This is a spurious
499 * link-down from the MII polling race (see
500 * PR 252165). Restore IFM_ACTIVE so the
501 * subsequent MIIBUS_LINKCHG check in
502 * mii_phy_update sees no change.
503 */
504 device_printf(dev,
505 "spurious link down (PHY link up), overriding\n");
506 sc->sc_flags |= URE_FLAG_LINK;
507 mii->mii_media_status |= IFM_ACTIVE;
508 }
509 }
510 done:
511 if (!locked)
512 URE_UNLOCK(sc);
513 }
514
515 static void
ure_miibus_linkchg(device_t dev)516 ure_miibus_linkchg(device_t dev)
517 {
518 struct ure_softc *sc;
519 struct mii_data *mii;
520 int locked;
521 uint16_t bmsr;
522
523 sc = device_get_softc(dev);
524 mii = GET_MII(sc);
525 locked = mtx_owned(&sc->sc_mtx);
526 if (locked == 0)
527 URE_LOCK(sc);
528
529 /*
530 * This is called by the default miibus linkchg handler
531 * before it calls if_link_state_change(). If the PHY
532 * still has link but the MII layer lost IFM_ACTIVE due
533 * to the polling race (see PR 252165), restore it so the
534 * notification goes out as LINK_STATE_UP rather than DOWN.
535 */
536 if (mii != NULL && (mii->mii_media_status & IFM_ACTIVE) == 0) {
537 (void)ure_ocp_reg_read(sc,
538 URE_OCP_BASE_MII + MII_BMSR * 2);
539 bmsr = ure_ocp_reg_read(sc,
540 URE_OCP_BASE_MII + MII_BMSR * 2);
541 if (bmsr & BMSR_LINK)
542 mii->mii_media_status |= IFM_ACTIVE;
543 }
544
545 if (locked == 0)
546 URE_UNLOCK(sc);
547 }
548
549 /*
550 * Probe for a RTL8152/RTL8153/RTL8156 chip.
551 */
552 static int
ure_probe(device_t dev)553 ure_probe(device_t dev)
554 {
555 struct usb_attach_arg *uaa;
556
557 uaa = device_get_ivars(dev);
558 if (uaa->usb_mode != USB_MODE_HOST)
559 return (ENXIO);
560 if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
561 return (ENXIO);
562
563 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
564 }
565
566 /*
567 * Attach the interface. Allocate softc structures, do ifmedia
568 * setup and ethernet/BPF attach.
569 */
570 static int
ure_attach(device_t dev)571 ure_attach(device_t dev)
572 {
573 struct usb_attach_arg *uaa = device_get_ivars(dev);
574 struct ure_softc *sc = device_get_softc(dev);
575 struct usb_ether *ue = &sc->sc_ue;
576 struct usb_config ure_config_rx[URE_MAX_RX];
577 struct usb_config ure_config_tx[URE_MAX_TX];
578 uint8_t iface_index;
579 int error;
580 int i;
581
582 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
583 device_set_usb_desc(dev);
584 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
585
586 iface_index = URE_IFACE_IDX;
587
588 if (sc->sc_flags & (URE_FLAG_8153 | URE_FLAG_8153B))
589 sc->sc_rxbufsz = URE_8153_RX_BUFSZ;
590 else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
591 sc->sc_rxbufsz = URE_8156_RX_BUFSZ;
592 else
593 sc->sc_rxbufsz = URE_8152_RX_BUFSZ;
594
595 for (i = 0; i < URE_MAX_RX; i++) {
596 ure_config_rx[i] = (struct usb_config) {
597 .type = UE_BULK,
598 .endpoint = UE_ADDR_ANY,
599 .direction = UE_DIR_IN,
600 .bufsize = sc->sc_rxbufsz,
601 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
602 .callback = ure_bulk_read_callback,
603 .timeout = 0, /* no timeout */
604 };
605 }
606 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_rx_xfer,
607 ure_config_rx, URE_MAX_RX, sc, &sc->sc_mtx);
608 if (error != 0) {
609 device_printf(dev, "allocating USB RX transfers failed\n");
610 goto detach;
611 }
612
613 for (i = 0; i < URE_MAX_TX; i++) {
614 ure_config_tx[i] = (struct usb_config) {
615 .type = UE_BULK,
616 .endpoint = UE_ADDR_ANY,
617 .direction = UE_DIR_OUT,
618 .bufsize = URE_TX_BUFSZ,
619 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
620 .callback = ure_bulk_write_callback,
621 .timeout = 10000, /* 10 seconds */
622 };
623 }
624 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_tx_xfer,
625 ure_config_tx, URE_MAX_TX, sc, &sc->sc_mtx);
626 if (error != 0) {
627 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX);
628 device_printf(dev, "allocating USB TX transfers failed\n");
629 goto detach;
630 }
631
632 ue->ue_sc = sc;
633 ue->ue_dev = dev;
634 ue->ue_udev = uaa->device;
635 ue->ue_mtx = &sc->sc_mtx;
636 ue->ue_methods = &ure_ue_methods;
637
638 error = uether_ifattach(ue);
639 if (error != 0) {
640 device_printf(dev, "could not attach interface\n");
641 goto detach;
642 }
643 return (0); /* success */
644
645 detach:
646 ure_detach(dev);
647 return (ENXIO); /* failure */
648 }
649
650 static int
ure_detach(device_t dev)651 ure_detach(device_t dev)
652 {
653 struct ure_softc *sc = device_get_softc(dev);
654 struct usb_ether *ue = &sc->sc_ue;
655
656 usbd_transfer_unsetup(sc->sc_tx_xfer, URE_MAX_TX);
657 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX);
658 uether_ifdetach(ue);
659 mtx_destroy(&sc->sc_mtx);
660
661 return (0);
662 }
663
664 /*
665 * Copy from USB buffers to a new mbuf chain with pkt header.
666 *
667 * This will use m_getm2 to get a mbuf chain w/ properly sized mbuf
668 * clusters as necessary.
669 */
670 static struct mbuf *
ure_makembuf(struct usb_page_cache * pc,usb_frlength_t offset,usb_frlength_t len)671 ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset,
672 usb_frlength_t len)
673 {
674 struct usb_page_search_res;
675 struct mbuf *m, *mb;
676 usb_frlength_t tlen;
677
678 m = m_getm2(NULL, len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR);
679 if (m == NULL)
680 return (m);
681
682 /* uether_newbuf does this. */
683 m_adj(m, ETHER_ALIGN);
684
685 m->m_pkthdr.len = len;
686
687 for (mb = m; len > 0; mb = mb->m_next) {
688 tlen = MIN(len, M_TRAILINGSPACE(mb));
689
690 usbd_copy_out(pc, offset, mtod(mb, uint8_t *), tlen);
691 mb->m_len = tlen;
692
693 offset += tlen;
694 len -= tlen;
695 }
696
697 return (m);
698 }
699
700 static void
ure_bulk_read_callback(struct usb_xfer * xfer,usb_error_t error)701 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
702 {
703 struct ure_softc *sc = usbd_xfer_softc(xfer);
704 struct usb_ether *ue = &sc->sc_ue;
705 if_t ifp = uether_getifp(ue);
706 struct usb_page_cache *pc;
707 struct mbuf *m;
708 struct ure_rxpkt pkt;
709 int actlen, off, len;
710 int caps;
711 uint32_t pktcsum;
712
713 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
714
715 switch (USB_GET_STATE(xfer)) {
716 case USB_ST_TRANSFERRED:
717 off = 0;
718 pc = usbd_xfer_get_frame(xfer, 0);
719 caps = if_getcapenable(ifp);
720 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb start\n");
721 while (actlen > 0) {
722 if (actlen < (int)(sizeof(pkt))) {
723 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
724 goto tr_setup;
725 }
726 usbd_copy_out(pc, off, &pkt, sizeof(pkt));
727
728 off += sizeof(pkt);
729 actlen -= sizeof(pkt);
730
731 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
732
733 DEVPRINTFN(13, sc->sc_ue.ue_dev,
734 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n",
735 pkt.ure_pktlen, pkt.ure_csum, pkt.ure_misc,
736 pkt.ure_rsvd2, pkt.ure_rsvd3, pkt.ure_rsvd4);
737 DEVPRINTFN(13, sc->sc_ue.ue_dev, "len: %d\n", len);
738
739 if (len >= URE_RXPKT_LEN_MASK) {
740 /*
741 * drop the rest of this segment. With out
742 * more information, we cannot know where next
743 * packet starts. Blindly continuing would
744 * cause a packet in packet attack, allowing
745 * one VLAN to inject packets w/o a VLAN tag,
746 * or injecting packets into other VLANs.
747 */
748 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
749 goto tr_setup;
750 }
751
752 if (actlen < len) {
753 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
754 goto tr_setup;
755 }
756
757 if (len >= (ETHER_HDR_LEN + ETHER_CRC_LEN))
758 m = ure_makembuf(pc, off, len - ETHER_CRC_LEN);
759 else
760 m = NULL;
761 if (m == NULL) {
762 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
763 } else {
764 /* make mbuf and queue */
765 pktcsum = le32toh(pkt.ure_csum);
766 if (caps & IFCAP_VLAN_HWTAGGING &&
767 pktcsum & URE_RXPKT_RX_VLAN_TAG) {
768 m->m_pkthdr.ether_vtag =
769 bswap16(pktcsum &
770 URE_RXPKT_VLAN_MASK);
771 m->m_flags |= M_VLANTAG;
772 }
773
774 /* set the necessary flags for rx checksum */
775 ure_rxcsum(caps, &pkt, m);
776
777 /*
778 * len has been known to be bogus at times,
779 * which leads to problems when passed to
780 * uether_rxmbuf(). Better understanding why we
781 * can get there make for good future work.
782 */
783 uether_rxmbuf(ue, m, 0);
784 }
785
786 off += roundup(len, URE_RXPKT_ALIGN);
787 actlen -= roundup(len, URE_RXPKT_ALIGN);
788 }
789 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb end\n");
790
791 /* FALLTHROUGH */
792 case USB_ST_SETUP:
793 tr_setup:
794 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
795 usbd_transfer_submit(xfer);
796 uether_rxflush(ue);
797 return;
798
799 default: /* Error */
800 DPRINTF("bulk read error, %s\n",
801 usbd_errstr(error));
802
803 if (error != USB_ERR_CANCELLED) {
804 /* try to clear stall first */
805 usbd_xfer_set_stall(xfer);
806 goto tr_setup;
807 }
808 return;
809 }
810 }
811
812 static void
ure_bulk_write_callback(struct usb_xfer * xfer,usb_error_t error)813 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
814 {
815 struct ure_softc *sc = usbd_xfer_softc(xfer);
816 if_t ifp = uether_getifp(&sc->sc_ue);
817 struct usb_page_cache *pc;
818 struct mbuf *m;
819 struct ure_txpkt txpkt;
820 uint32_t regtmp;
821 int len, pos;
822 int rem;
823 int caps;
824
825 switch (USB_GET_STATE(xfer)) {
826 case USB_ST_TRANSFERRED:
827 DPRINTFN(11, "transfer complete\n");
828 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
829
830 /* FALLTHROUGH */
831 case USB_ST_SETUP:
832 tr_setup:
833 if ((sc->sc_flags & URE_FLAG_LINK) == 0) {
834 /* don't send anything if there is no link! */
835 break;
836 }
837
838 pc = usbd_xfer_get_frame(xfer, 0);
839 caps = if_getcapenable(ifp);
840
841 pos = 0;
842 rem = URE_TX_BUFSZ;
843 while (rem > sizeof(txpkt)) {
844 m = if_dequeue(ifp);
845 if (m == NULL)
846 break;
847
848 /*
849 * make sure we don't ever send too large of a
850 * packet
851 */
852 len = m->m_pkthdr.len;
853 if ((len & URE_TXPKT_LEN_MASK) != len) {
854 device_printf(sc->sc_ue.ue_dev,
855 "pkt len too large: %#x", len);
856 pkterror:
857 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
858 m_freem(m);
859 continue;
860 }
861
862 if (sizeof(txpkt) +
863 roundup(len, URE_TXPKT_ALIGN) > rem) {
864 /* out of space */
865 if_sendq_prepend(ifp, m);
866 m = NULL;
867 break;
868 }
869
870 txpkt = (struct ure_txpkt){};
871 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
872 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
873 if (m->m_flags & M_VLANTAG) {
874 txpkt.ure_csum = htole32(
875 bswap16(m->m_pkthdr.ether_vtag &
876 URE_TXPKT_VLAN_MASK) | URE_TXPKT_VLAN);
877 }
878 if (ure_txcsum(m, caps, ®tmp)) {
879 device_printf(sc->sc_ue.ue_dev,
880 "pkt l4 off too large");
881 goto pkterror;
882 }
883 txpkt.ure_csum |= htole32(regtmp);
884
885 DEVPRINTFN(13, sc->sc_ue.ue_dev,
886 "txpkt: mbflg: %#x, %#x, %#x\n",
887 m->m_pkthdr.csum_flags, le32toh(txpkt.ure_pktlen),
888 le32toh(txpkt.ure_csum));
889
890 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
891
892 pos += sizeof(txpkt);
893 rem -= sizeof(txpkt);
894
895 usbd_m_copy_in(pc, pos, m, 0, len);
896
897 pos += roundup(len, URE_TXPKT_ALIGN);
898 rem -= roundup(len, URE_TXPKT_ALIGN);
899
900 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
901
902 /*
903 * If there's a BPF listener, bounce a copy
904 * of this frame to him.
905 */
906 BPF_MTAP(ifp, m);
907
908 m_freem(m);
909 }
910
911 /* no packets to send */
912 if (pos == 0)
913 break;
914
915 /* Set frame length. */
916 usbd_xfer_set_frame_len(xfer, 0, pos);
917
918 usbd_transfer_submit(xfer);
919
920 return;
921
922 default: /* Error */
923 DPRINTFN(11, "transfer error, %s\n",
924 usbd_errstr(error));
925
926 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
927 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
928
929 if (error == USB_ERR_TIMEOUT) {
930 DEVPRINTFN(12, sc->sc_ue.ue_dev,
931 "pkt tx timeout\n");
932 }
933
934 if (error != USB_ERR_CANCELLED) {
935 /* try to clear stall first */
936 usbd_xfer_set_stall(xfer);
937 goto tr_setup;
938 }
939 }
940 }
941
942 static void
ure_read_chipver(struct ure_softc * sc)943 ure_read_chipver(struct ure_softc *sc)
944 {
945 uint16_t ver;
946
947 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
948 sc->sc_ver = ver;
949 switch (ver) {
950 case 0x4c00:
951 sc->sc_chip |= URE_CHIP_VER_4C00;
952 sc->sc_flags = URE_FLAG_8152;
953 break;
954 case 0x4c10:
955 sc->sc_chip |= URE_CHIP_VER_4C10;
956 sc->sc_flags = URE_FLAG_8152;
957 break;
958 case 0x5c00:
959 sc->sc_chip |= URE_CHIP_VER_5C00;
960 sc->sc_flags = URE_FLAG_8153;
961 break;
962 case 0x5c10:
963 sc->sc_chip |= URE_CHIP_VER_5C10;
964 sc->sc_flags = URE_FLAG_8153;
965 break;
966 case 0x5c20:
967 sc->sc_chip |= URE_CHIP_VER_5C20;
968 sc->sc_flags = URE_FLAG_8153;
969 break;
970 case 0x5c30:
971 sc->sc_chip |= URE_CHIP_VER_5C30;
972 sc->sc_flags = URE_FLAG_8153;
973 break;
974 case 0x6000:
975 sc->sc_flags = URE_FLAG_8153B;
976 sc->sc_chip |= URE_CHIP_VER_6000;
977 break;
978 case 0x6010:
979 sc->sc_flags = URE_FLAG_8153B;
980 sc->sc_chip |= URE_CHIP_VER_6010;
981 break;
982 case 0x7020:
983 sc->sc_flags = URE_FLAG_8156;
984 sc->sc_chip |= URE_CHIP_VER_7020;
985 break;
986 case 0x7030:
987 sc->sc_flags = URE_FLAG_8156;
988 sc->sc_chip |= URE_CHIP_VER_7030;
989 break;
990 case 0x7400:
991 sc->sc_flags = URE_FLAG_8156B;
992 sc->sc_chip |= URE_CHIP_VER_7400;
993 break;
994 case 0x7410:
995 sc->sc_flags = URE_FLAG_8156B;
996 sc->sc_chip |= URE_CHIP_VER_7410;
997 break;
998 default:
999 device_printf(sc->sc_ue.ue_dev,
1000 "unknown version 0x%04x\n", ver);
1001 break;
1002 }
1003 }
1004
1005 static int
ure_sysctl_chipver(SYSCTL_HANDLER_ARGS)1006 ure_sysctl_chipver(SYSCTL_HANDLER_ARGS)
1007 {
1008 struct sbuf sb;
1009 struct ure_softc *sc = arg1;
1010 int error;
1011
1012 sbuf_new_for_sysctl(&sb, NULL, 0, req);
1013
1014 sbuf_printf(&sb, "%04x", sc->sc_ver);
1015
1016 error = sbuf_finish(&sb);
1017 sbuf_delete(&sb);
1018
1019 return (error);
1020 }
1021
1022 static void
ure_attach_post(struct usb_ether * ue)1023 ure_attach_post(struct usb_ether *ue)
1024 {
1025 struct ure_softc *sc = uether_getsc(ue);
1026
1027 sc->sc_rxstarted = 0;
1028 sc->sc_phyno = 0;
1029
1030 /* Determine the chip version. */
1031 ure_read_chipver(sc);
1032
1033 /* Initialize controller and get station address. */
1034 if (sc->sc_flags & URE_FLAG_8152)
1035 ure_rtl8152_init(sc);
1036 else if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
1037 ure_rtl8153b_init(sc);
1038 else
1039 ure_rtl8153_init(sc);
1040
1041 if ((sc->sc_chip & URE_CHIP_VER_4C00) ||
1042 (sc->sc_chip & URE_CHIP_VER_4C10))
1043 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
1044 ue->ue_eaddr, 8);
1045 else
1046 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
1047 ue->ue_eaddr, 8);
1048
1049 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) {
1050 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n");
1051 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0);
1052 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */
1053 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */
1054 }
1055 }
1056
1057 static int
ure_attach_post_sub(struct usb_ether * ue)1058 ure_attach_post_sub(struct usb_ether *ue)
1059 {
1060 struct sysctl_ctx_list *sctx;
1061 struct sysctl_oid *soid;
1062 struct ure_softc *sc;
1063 if_t ifp;
1064 int error;
1065
1066 sc = uether_getsc(ue);
1067 ifp = ue->ue_ifp;
1068 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1069 if_setstartfn(ifp, uether_start);
1070 if_setioctlfn(ifp, ure_ioctl);
1071 if_setinitfn(ifp, uether_init);
1072 /*
1073 * Try to keep two transfers full at a time.
1074 * ~(TRANSFER_SIZE / 80 bytes/pkt * 2 buffers in flight)
1075 */
1076 if_setsendqlen(ifp, 512);
1077 if_setsendqready(ifp);
1078
1079 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1080 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0);
1081 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0);
1082 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP);
1083 #ifdef INET6
1084 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0);
1085 if_sethwassistbits(ifp, CSUM_IP6_UDP|CSUM_IP6_TCP, 0);
1086 #endif
1087 if_setcapenable(ifp, if_getcapabilities(ifp));
1088
1089 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1090 ifmedia_init(&sc->sc_ifmedia, IFM_IMASK, ure_ifmedia_upd,
1091 ure_ifmedia_sts);
1092 ure_add_media_types(sc);
1093 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1094 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO);
1095 sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
1096 error = 0;
1097 } else {
1098 bus_topo_lock();
1099 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
1100 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
1101 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
1102 bus_topo_unlock();
1103 }
1104
1105 sctx = device_get_sysctl_ctx(sc->sc_ue.ue_dev);
1106 soid = device_get_sysctl_tree(sc->sc_ue.ue_dev);
1107 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "chipver",
1108 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
1109 ure_sysctl_chipver, "A",
1110 "Return string with chip version.");
1111
1112 return (error);
1113 }
1114
1115 static void
ure_init(struct usb_ether * ue)1116 ure_init(struct usb_ether *ue)
1117 {
1118 struct ure_softc *sc = uether_getsc(ue);
1119 if_t ifp = uether_getifp(ue);
1120 uint16_t cpcr;
1121 uint32_t reg;
1122
1123 URE_LOCK_ASSERT(sc, MA_OWNED);
1124
1125 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1126 return;
1127
1128 /* Cancel pending I/O. */
1129 ure_stop(ue);
1130
1131 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
1132 ure_rtl8153b_nic_reset(sc);
1133 else
1134 ure_reset(sc);
1135
1136 /* Set MAC address. */
1137 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1138 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
1139 if_getlladdr(ifp), 8);
1140 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1141
1142 /* Set RX EARLY timeout and size */
1143 if (sc->sc_flags & URE_FLAG_8153) {
1144 switch (usbd_get_speed(sc->sc_ue.ue_udev)) {
1145 case USB_SPEED_SUPER:
1146 reg = URE_COALESCE_SUPER / 8;
1147 break;
1148 case USB_SPEED_HIGH:
1149 reg = URE_COALESCE_HIGH / 8;
1150 break;
1151 default:
1152 reg = URE_COALESCE_SLOW / 8;
1153 break;
1154 }
1155 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, reg);
1156 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1157 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1158 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 4);
1159 } else if (sc->sc_flags & URE_FLAG_8153B) {
1160 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 158);
1161 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875);
1162 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1163 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1164 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);
1165 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB,
1166 URE_OWN_UPDATE | URE_OWN_CLEAR);
1167 } else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1168 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 80);
1169 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875);
1170 reg = URE_8156_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1171 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1172 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);
1173 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB,
1174 URE_OWN_UPDATE | URE_OWN_CLEAR);
1175 }
1176
1177 if (sc->sc_flags & URE_FLAG_8156B) {
1178 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1179 uether_pause(&sc->sc_ue, hz / 500);
1180 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1181 }
1182
1183 /* Reset the packet filter. */
1184 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
1185 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
1186
1187 /* Enable RX VLANs if enabled */
1188 cpcr = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA);
1189 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1190 DEVPRINTFN(12, sc->sc_ue.ue_dev, "enabled hw vlan tag\n");
1191 cpcr |= URE_CPCR_RX_VLAN;
1192 } else {
1193 DEVPRINTFN(12, sc->sc_ue.ue_dev, "disabled hw vlan tag\n");
1194 cpcr &= ~URE_CPCR_RX_VLAN;
1195 }
1196 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, cpcr);
1197
1198 /* Enable transmit and receive. */
1199 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE);
1200
1201 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1202
1203 /* Configure RX filters. */
1204 ure_rxfilter(ue);
1205
1206 usbd_xfer_set_stall(sc->sc_tx_xfer[0]);
1207
1208 /* Indicate we are up and running. */
1209 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1210
1211 /* Switch to selected media. */
1212 ure_ifmedia_upd(ifp);
1213 }
1214
1215 static void
ure_tick(struct usb_ether * ue)1216 ure_tick(struct usb_ether *ue)
1217 {
1218 struct ure_softc *sc = uether_getsc(ue);
1219 if_t ifp = uether_getifp(ue);
1220 struct mii_data *mii;
1221
1222 URE_LOCK_ASSERT(sc, MA_OWNED);
1223
1224 (void)ifp;
1225 for (int i = 0; i < URE_MAX_RX; i++)
1226 DEVPRINTFN(13, sc->sc_ue.ue_dev,
1227 "rx[%d] = %d\n", i, USB_GET_STATE(sc->sc_rx_xfer[i]));
1228
1229 for (int i = 0; i < URE_MAX_TX; i++)
1230 DEVPRINTFN(13, sc->sc_ue.ue_dev,
1231 "tx[%d] = %d\n", i, USB_GET_STATE(sc->sc_tx_xfer[i]));
1232
1233 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1234 ure_link_state(sc);
1235 } else {
1236 mii = GET_MII(sc);
1237 mii_tick(mii);
1238 if ((sc->sc_flags & URE_FLAG_LINK) == 0
1239 && mii->mii_media_status & IFM_ACTIVE &&
1240 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1241 sc->sc_flags |= URE_FLAG_LINK;
1242 sc->sc_rxstarted = 0;
1243 ure_start(ue);
1244 }
1245 }
1246 }
1247
1248 static u_int
ure_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1249 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1250 {
1251 uint32_t h, *hashes = arg;
1252
1253 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
1254 if (h < 32)
1255 hashes[0] |= (1 << h);
1256 else
1257 hashes[1] |= (1 << (h - 32));
1258 return (1);
1259 }
1260
1261 /*
1262 * Program the 64-bit multicast hash filter.
1263 */
1264 static void
ure_rxfilter(struct usb_ether * ue)1265 ure_rxfilter(struct usb_ether *ue)
1266 {
1267 struct ure_softc *sc = uether_getsc(ue);
1268 if_t ifp = uether_getifp(ue);
1269 uint32_t rxmode;
1270 uint32_t h, hashes[2] = { 0, 0 };
1271
1272 URE_LOCK_ASSERT(sc, MA_OWNED);
1273
1274 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA);
1275 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM);
1276 rxmode |= URE_RCR_APM; /* accept physical match packets */
1277 rxmode |= URE_RCR_AB; /* always accept broadcasts */
1278 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) {
1279 if (if_getflags(ifp) & IFF_PROMISC)
1280 rxmode |= URE_RCR_AAP;
1281 rxmode |= URE_RCR_AM;
1282 hashes[0] = hashes[1] = 0xffffffff;
1283 goto done;
1284 }
1285
1286 /* calculate multicast masks */
1287 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes);
1288
1289 h = bswap32(hashes[0]);
1290 hashes[0] = bswap32(hashes[1]);
1291 hashes[1] = h;
1292 rxmode |= URE_RCR_AM; /* accept multicast packets */
1293
1294 done:
1295 DEVPRINTFN(14, ue->ue_dev, "rxfilt: RCR: %#x\n",
1296 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
1297 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
1298 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
1299 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
1300 }
1301
1302 static void
ure_start(struct usb_ether * ue)1303 ure_start(struct usb_ether *ue)
1304 {
1305 struct ure_softc *sc = uether_getsc(ue);
1306 unsigned i;
1307
1308 URE_LOCK_ASSERT(sc, MA_OWNED);
1309
1310 if (!sc->sc_rxstarted) {
1311 sc->sc_rxstarted = 1;
1312 for (i = 0; i != URE_MAX_RX; i++)
1313 usbd_transfer_start(sc->sc_rx_xfer[i]);
1314 }
1315
1316 for (i = 0; i != URE_MAX_TX; i++)
1317 usbd_transfer_start(sc->sc_tx_xfer[i]);
1318 }
1319
1320 static void
ure_reset(struct ure_softc * sc)1321 ure_reset(struct ure_softc *sc)
1322 {
1323 int i;
1324
1325 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
1326
1327 for (i = 0; i < URE_TIMEOUT; i++) {
1328 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
1329 URE_CR_RST))
1330 break;
1331 uether_pause(&sc->sc_ue, hz / 100);
1332 }
1333 if (i == URE_TIMEOUT)
1334 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
1335 }
1336
1337 /*
1338 * Set media options.
1339 */
1340 static int
ure_ifmedia_upd(if_t ifp)1341 ure_ifmedia_upd(if_t ifp)
1342 {
1343 struct ure_softc *sc = if_getsoftc(ifp);
1344 struct ifmedia *ifm;
1345 struct mii_data *mii;
1346 struct mii_softc *miisc;
1347 int gig;
1348 int reg;
1349 int anar;
1350 int locked;
1351 int error;
1352
1353 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1354 ifm = &sc->sc_ifmedia;
1355 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1356 return (EINVAL);
1357
1358 locked = mtx_owned(&sc->sc_mtx);
1359 if (!locked)
1360 URE_LOCK(sc);
1361 reg = ure_ocp_reg_read(sc, 0xa5d4);
1362 reg &= ~URE_ADV_2500TFDX;
1363
1364 anar = gig = 0;
1365 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1366 case IFM_AUTO:
1367 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1368 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1369 reg |= URE_ADV_2500TFDX;
1370 break;
1371 case IFM_2500_T:
1372 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1373 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1374 reg |= URE_ADV_2500TFDX;
1375 if_setbaudrate(ifp, IF_Mbps(2500));
1376 break;
1377 case IFM_1000_T:
1378 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1379 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1380 if_setbaudrate(ifp, IF_Gbps(1));
1381 break;
1382 case IFM_100_TX:
1383 anar |= ANAR_TX | ANAR_TX_FD;
1384 if_setbaudrate(ifp, IF_Mbps(100));
1385 break;
1386 case IFM_10_T:
1387 anar |= ANAR_10 | ANAR_10_FD;
1388 if_setbaudrate(ifp, IF_Mbps(10));
1389 break;
1390 default:
1391 device_printf(sc->sc_ue.ue_dev, "unsupported media type\n");
1392 if (!locked)
1393 URE_UNLOCK(sc);
1394 return (EINVAL);
1395 }
1396
1397 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2,
1398 anar | ANAR_PAUSE_ASYM | ANAR_FC);
1399 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig);
1400 ure_ocp_reg_write(sc, 0xa5d4, reg);
1401 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR,
1402 BMCR_AUTOEN | BMCR_STARTNEG);
1403 if (!locked)
1404 URE_UNLOCK(sc);
1405 return (0);
1406 }
1407
1408 mii = GET_MII(sc);
1409
1410 URE_LOCK_ASSERT(sc, MA_OWNED);
1411 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1412 PHY_RESET(miisc);
1413 error = mii_mediachg(mii);
1414 return (error);
1415 }
1416
1417 /*
1418 * Report current media status.
1419 */
1420 static void
ure_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1421 ure_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1422 {
1423 struct ure_softc *sc;
1424 struct mii_data *mii;
1425 uint16_t status;
1426
1427 sc = if_getsoftc(ifp);
1428 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1429 URE_LOCK(sc);
1430 ifmr->ifm_status = IFM_AVALID;
1431 if (ure_get_link_status(sc)) {
1432 ifmr->ifm_status |= IFM_ACTIVE;
1433 status = ure_read_2(sc, URE_PLA_PHYSTATUS,
1434 URE_MCU_TYPE_PLA);
1435 if ((status & URE_PHYSTATUS_FDX) ||
1436 (status & URE_PHYSTATUS_2500MBPS))
1437 ifmr->ifm_active |= IFM_FDX;
1438 else
1439 ifmr->ifm_active |= IFM_HDX;
1440 if (status & URE_PHYSTATUS_10MBPS)
1441 ifmr->ifm_active |= IFM_10_T;
1442 else if (status & URE_PHYSTATUS_100MBPS)
1443 ifmr->ifm_active |= IFM_100_TX;
1444 else if (status & URE_PHYSTATUS_1000MBPS)
1445 ifmr->ifm_active |= IFM_1000_T;
1446 else if (status & URE_PHYSTATUS_2500MBPS)
1447 ifmr->ifm_active |= IFM_2500_T;
1448 }
1449 URE_UNLOCK(sc);
1450 return;
1451 }
1452
1453 mii = GET_MII(sc);
1454
1455 URE_LOCK(sc);
1456 mii_pollstat(mii);
1457 ifmr->ifm_active = mii->mii_media_active;
1458 ifmr->ifm_status = mii->mii_media_status;
1459 URE_UNLOCK(sc);
1460 }
1461
1462 static void
ure_add_media_types(struct ure_softc * sc)1463 ure_add_media_types(struct ure_softc *sc)
1464 {
1465 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
1466 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1467 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
1468 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1469 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1470 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL);
1471 }
1472
1473 static void
ure_link_state(struct ure_softc * sc)1474 ure_link_state(struct ure_softc *sc)
1475 {
1476 if_t ifp = uether_getifp(&sc->sc_ue);
1477
1478 if (ure_get_link_status(sc)) {
1479 if (if_getlinkstate(ifp) != LINK_STATE_UP) {
1480 if_link_state_change(ifp, LINK_STATE_UP);
1481 /* Enable transmit and receive. */
1482 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE);
1483
1484 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1485 URE_PHYSTATUS_2500MBPS)
1486 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);
1487 else
1488 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);
1489 }
1490 } else {
1491 if (if_getlinkstate(ifp) != LINK_STATE_DOWN) {
1492 if_link_state_change(ifp, LINK_STATE_DOWN);
1493 }
1494 }
1495 }
1496
1497 static int
ure_get_link_status(struct ure_softc * sc)1498 ure_get_link_status(struct ure_softc *sc)
1499 {
1500 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1501 URE_PHYSTATUS_LINK) {
1502 sc->sc_flags |= URE_FLAG_LINK;
1503 return (1);
1504 } else {
1505 sc->sc_flags &= ~URE_FLAG_LINK;
1506 return (0);
1507 }
1508 }
1509
1510 static int
ure_ioctl(if_t ifp,u_long cmd,caddr_t data)1511 ure_ioctl(if_t ifp, u_long cmd, caddr_t data)
1512 {
1513 struct usb_ether *ue = if_getsoftc(ifp);
1514 struct ure_softc *sc;
1515 struct ifreq *ifr;
1516 int error, mask, reinit;
1517
1518 sc = uether_getsc(ue);
1519 ifr = (struct ifreq *)data;
1520 error = 0;
1521 reinit = 0;
1522 switch (cmd) {
1523 case SIOCSIFCAP:
1524 URE_LOCK(sc);
1525 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1526 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1527 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1528 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1529 reinit++;
1530 }
1531 if ((mask & IFCAP_TXCSUM) != 0 &&
1532 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1533 if_togglecapenable(ifp, IFCAP_TXCSUM);
1534 if_togglehwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP);
1535 }
1536 if ((mask & IFCAP_RXCSUM) != 0 &&
1537 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
1538 if_togglecapenable(ifp, IFCAP_RXCSUM);
1539 }
1540 if ((mask & IFCAP_TXCSUM_IPV6) != 0 &&
1541 (if_getcapabilities(ifp) & IFCAP_TXCSUM_IPV6) != 0) {
1542 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6);
1543 if_togglehwassist(ifp, CSUM_IP6_UDP|CSUM_IP6_TCP);
1544 }
1545 if ((mask & IFCAP_RXCSUM_IPV6) != 0 &&
1546 (if_getcapabilities(ifp) & IFCAP_RXCSUM_IPV6) != 0) {
1547 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6);
1548 }
1549 if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1550 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1551 else
1552 reinit = 0;
1553 URE_UNLOCK(sc);
1554 if (reinit > 0)
1555 uether_init(ue);
1556 break;
1557
1558 case SIOCSIFMTU:
1559 /*
1560 * in testing large MTUs "crashes" the device, it
1561 * leaves the device w/ a broken state where link
1562 * is in a bad state.
1563 */
1564 if (ifr->ifr_mtu < ETHERMIN ||
1565 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN -
1566 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) {
1567 error = EINVAL;
1568 break;
1569 }
1570 URE_LOCK(sc);
1571 if (if_getmtu(ifp) != ifr->ifr_mtu)
1572 if_setmtu(ifp, ifr->ifr_mtu);
1573 URE_UNLOCK(sc);
1574 break;
1575
1576 case SIOCGIFMEDIA:
1577 case SIOCSIFMEDIA:
1578 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
1579 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
1580 else
1581 error = uether_ioctl(ifp, cmd, data);
1582 break;
1583
1584 default:
1585 error = uether_ioctl(ifp, cmd, data);
1586 break;
1587 }
1588
1589 return (error);
1590 }
1591
1592 static void
ure_rtl8152_init(struct ure_softc * sc)1593 ure_rtl8152_init(struct ure_softc *sc)
1594 {
1595 uint32_t pwrctrl;
1596
1597 ure_enable_aldps(sc, false);
1598
1599 if (sc->sc_chip & URE_CHIP_VER_4C00) {
1600 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK);
1601 }
1602
1603 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT);
1604
1605 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, URE_RESUME_INDICATE);
1606
1607 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
1608
1609 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
1610 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
1611 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
1612 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
1613 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
1614 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
1615 URE_SPDWN_LINKCHG_MSK);
1616
1617 /* Enable Rx aggregation. */
1618 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1619
1620 ure_enable_aldps(sc, false);
1621
1622 ure_rtl8152_nic_reset(sc);
1623
1624 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
1625 URE_TX_AGG_MAX_THRESHOLD);
1626 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
1627 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
1628 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
1629 }
1630
1631 static void
ure_rtl8153_init(struct ure_softc * sc)1632 ure_rtl8153_init(struct ure_softc *sc)
1633 {
1634 uint16_t val;
1635 uint8_t u1u2[8];
1636 int i;
1637
1638 ure_enable_aldps(sc, false);
1639
1640 memset(u1u2, 0x00, sizeof(u1u2));
1641 ure_write_mem(sc, URE_USB_TOLERANCE,
1642 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1643
1644 for (i = 0; i < URE_TIMEOUT; i++) {
1645 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1646 URE_AUTOLOAD_DONE)
1647 break;
1648 uether_pause(&sc->sc_ue, hz / 100);
1649 }
1650 if (i == URE_TIMEOUT)
1651 device_printf(sc->sc_ue.ue_dev,
1652 "timeout waiting for chip autoload\n");
1653
1654 for (i = 0; i < URE_TIMEOUT; i++) {
1655 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
1656 URE_PHY_STAT_MASK;
1657 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
1658 break;
1659 uether_pause(&sc->sc_ue, hz / 100);
1660 }
1661 if (i == URE_TIMEOUT)
1662 device_printf(sc->sc_ue.ue_dev,
1663 "timeout waiting for phy to stabilize\n");
1664
1665 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1666
1667 if (sc->sc_chip & URE_CHIP_VER_5C10) {
1668 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1669 val &= ~URE_PWD_DN_SCALE_MASK;
1670 val |= URE_PWD_DN_SCALE(96);
1671 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
1672
1673 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1674 } else if (sc->sc_chip & URE_CHIP_VER_5C20)
1675 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, URE_ECM_ALDPS);
1676
1677 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1678 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
1679 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
1680 0)
1681 val &= ~URE_DYNAMIC_BURST;
1682 else
1683 val |= URE_DYNAMIC_BURST;
1684 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
1685 }
1686
1687 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC);
1688
1689 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN);
1690
1691 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK);
1692
1693 if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
1694 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
1695 val = URE_LPM_TIMER_500MS;
1696 else
1697 val = URE_LPM_TIMER_500US;
1698 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1699 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
1700
1701 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1702 val &= ~URE_SEN_VAL_MASK;
1703 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1704 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
1705
1706 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1707
1708 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN | URE_PHASE2_EN);
1709
1710 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1711
1712 memset(u1u2, 0xff, sizeof(u1u2));
1713 ure_write_mem(sc, URE_USB_TOLERANCE,
1714 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1715
1716 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
1717 URE_ALDPS_SPDWN_RATIO);
1718 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1719 URE_EEE_SPDWN_RATIO);
1720 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1721 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
1722 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
1723 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
1724 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
1725 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
1726 URE_EEE_SPDWN_EN);
1727
1728 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1729 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1730 val |= URE_U2P3_ENABLE;
1731 else
1732 val &= ~URE_U2P3_ENABLE;
1733 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1734
1735 memset(u1u2, 0x00, sizeof(u1u2));
1736 ure_write_mem(sc, URE_USB_TOLERANCE,
1737 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1738
1739 ure_enable_aldps(sc, false);
1740
1741 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1742 URE_CHIP_VER_5C20)) {
1743 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
1744 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1745 }
1746 if (sc->sc_chip & URE_CHIP_VER_5C00) {
1747 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
1748 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
1749 ~URE_CTAP_SHORT_EN);
1750 }
1751 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1752 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1753 URE_EEE_CLKDIV_EN);
1754 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
1755 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
1756 URE_EN_10M_BGOFF);
1757 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1758 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1759 URE_EN_10M_PLLOFF);
1760 ure_sram_write(sc, URE_SRAM_IMPEDANCE, 0x0b13);
1761 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_PFM_PWM_SWITCH);
1762
1763 /* Enable LPF corner auto tune. */
1764 ure_sram_write(sc, URE_SRAM_LPF_CFG, 0xf70f);
1765
1766 /* Adjust 10M amplitude. */
1767 ure_sram_write(sc, URE_SRAM_10M_AMP1, 0x00af);
1768 ure_sram_write(sc, URE_SRAM_10M_AMP2, 0x0208);
1769
1770 ure_rtl8152_nic_reset(sc);
1771
1772 /* Enable Rx aggregation. */
1773 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1774
1775 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1776 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1777 val |= URE_U2P3_ENABLE;
1778 else
1779 val &= ~URE_U2P3_ENABLE;
1780 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1781
1782 memset(u1u2, 0xff, sizeof(u1u2));
1783 ure_write_mem(sc, URE_USB_TOLERANCE,
1784 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1785 }
1786
1787 static void
ure_rtl8153b_init(struct ure_softc * sc)1788 ure_rtl8153b_init(struct ure_softc *sc)
1789 {
1790 uint16_t val;
1791 int i;
1792
1793 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1794 URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01);
1795 ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0);
1796 URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020);
1797 }
1798
1799 if (sc->sc_flags & URE_FLAG_8156B) {
1800 URE_SETBIT_2(sc, 0xb460, URE_MCU_TYPE_USB, 0x08);
1801 }
1802
1803 ure_enable_aldps(sc, false);
1804
1805 /* Disable U1U2 */
1806 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1807
1808 /* Wait loading flash */
1809 if (sc->sc_chip == URE_CHIP_VER_7410) {
1810 if ((ure_read_2(sc, 0xd3ae, URE_MCU_TYPE_PLA) & 0x0002) &&
1811 !(ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0020)) {
1812 for (i=0; i < 100; i++) {
1813 if (ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0004)
1814 break;
1815 uether_pause(&sc->sc_ue, hz / 1000);
1816 }
1817 }
1818 }
1819
1820 for (i = 0; i < URE_TIMEOUT; i++) {
1821 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1822 URE_AUTOLOAD_DONE)
1823 break;
1824 uether_pause(&sc->sc_ue, hz / 100);
1825 }
1826 if (i == URE_TIMEOUT)
1827 device_printf(sc->sc_ue.ue_dev,
1828 "timeout waiting for chip autoload\n");
1829
1830 val = ure_phy_status(sc, 0);
1831 if ((val == URE_PHY_STAT_EXT_INIT) &
1832 (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) {
1833 ure_ocp_reg_write(sc, 0xa468,
1834 ure_ocp_reg_read(sc, 0xa468) & ~0x0a);
1835 if (sc->sc_flags & URE_FLAG_8156B)
1836 ure_ocp_reg_write(sc, 0xa466,
1837 ure_ocp_reg_read(sc, 0xa466) & ~0x01);
1838 }
1839
1840 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + MII_BMCR);
1841 if (val & BMCR_PDOWN) {
1842 val &= ~BMCR_PDOWN;
1843 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, val);
1844 }
1845
1846 ure_phy_status(sc, URE_PHY_STAT_LAN_ON);
1847
1848 /* Disable U2P3 */
1849 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1850
1851 /* MSC timer, 32760 ms. */
1852 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff);
1853
1854 /* U1/U2/L1 idle timer, 500 us. */
1855 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500);
1856
1857 /* Disable power cut */
1858 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN);
1859 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1860
1861 /* Disable ups */
1862 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_UPS_EN | URE_USP_PREWAKE);
1863 URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01);
1864
1865 /* Disable queue wake */
1866 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_USB, URE_UPCOMING_RUNTIME_D3);
1867 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_USB, URE_LINK_CHG_EVENT);
1868 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_USB, URE_LINK_CHANGE_FLAG);
1869
1870 /* Disable runtime suspend */
1871 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1872 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_USB, URE_LINK_OFF_WAKE_EN);
1873 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1874
1875 /* Enable U1U2 */
1876 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER)
1877 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1878
1879 if (sc->sc_flags & URE_FLAG_8156B) {
1880 URE_CLRBIT_2(sc, 0xc010, URE_MCU_TYPE_PLA, 0x0800);
1881 URE_SETBIT_2(sc, 0xe854, URE_MCU_TYPE_PLA, 0x0001);
1882
1883 /* enable fc timer and set timer to 600 ms. */
1884 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, URE_CTRL_TIMER_EN | (600 / 8));
1885
1886 if (!(ure_read_1(sc, 0xdc6b, URE_MCU_TYPE_PLA) & 0x80)) {
1887 val = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB);
1888 val |= URE_FLOW_CTRL_PATCH_OPT | 0x0100;
1889 val &= ~0x08;
1890 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, val);
1891 }
1892
1893 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1894 }
1895
1896 val = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA);
1897 if (ure_get_link_status(sc))
1898 val |= URE_CUR_LINK_OK;
1899 else
1900 val &= ~URE_CUR_LINK_OK;
1901 val |= URE_POLL_LINK_CHG;
1902 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, val);
1903
1904 /* MAC clock speed down */
1905 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1906 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403);
1907 val = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA);
1908 val &= ~0xff;
1909 val |= URE_MAC_CLK_SPDWN_EN | 0x03;
1910 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, val);
1911 } else {
1912 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_USB, URE_MAC_CLK_SPDWN_EN);
1913 }
1914 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN);
1915
1916 /* Enable Rx aggregation. */
1917 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1918
1919 if (sc->sc_flags & URE_FLAG_8156)
1920 URE_SETBIT_1(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x02);
1921
1922 /* Reset tally */
1923 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_USB, URE_TALLY_RESET);
1924 }
1925
1926 static void
ure_rtl8153b_nic_reset(struct ure_softc * sc)1927 ure_rtl8153b_nic_reset(struct ure_softc *sc)
1928 {
1929 if_t ifp = uether_getifp(&sc->sc_ue);
1930 uint16_t val;
1931 int i;
1932
1933 /* Disable U1U2 */
1934 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1935
1936 /* Disable U2P3 */
1937 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1938
1939 ure_enable_aldps(sc, false);
1940
1941 /* Enable rxdy_gated */
1942 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1943
1944 /* Disable teredo */
1945 ure_disable_teredo(sc);
1946
1947 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8153b_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
1948 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
1949
1950 ure_reset(sc);
1951
1952 /* Reset BMU */
1953 URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT);
1954 URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT);
1955
1956 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
1957 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
1958 if (sc->sc_flags & URE_FLAG_8153B) {
1959 for (i = 0; i < URE_TIMEOUT; i++) {
1960 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1961 URE_LINK_LIST_READY)
1962 break;
1963 uether_pause(&sc->sc_ue, hz / 100);
1964 }
1965 if (i == URE_TIMEOUT)
1966 device_printf(sc->sc_ue.ue_dev,
1967 "timeout waiting for OOB control\n");
1968
1969 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL);
1970 for (i = 0; i < URE_TIMEOUT; i++) {
1971 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1972 URE_LINK_LIST_READY)
1973 break;
1974 uether_pause(&sc->sc_ue, hz / 100);
1975 }
1976 if (i == URE_TIMEOUT)
1977 device_printf(sc->sc_ue.ue_dev,
1978 "timeout waiting for OOB control\n");
1979 }
1980
1981 /* Configure rxvlan */
1982 val = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA);
1983 val &= ~0x00c0;
1984 if (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING)
1985 val |= 0x00c0;
1986 ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, val);
1987
1988 val = if_getmtu(ifp);
1989 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, URE_FRAMELEN(val));
1990 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, URE_MTPS_JUMBO);
1991
1992 if (sc->sc_flags & URE_FLAG_8153B) {
1993 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO);
1994 ure_reset(sc);
1995 }
1996
1997 /* Configure fc parameter */
1998 if (sc->sc_flags & URE_FLAG_8156) {
1999 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0400);
2000 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0800);
2001 } else if (sc->sc_flags & URE_FLAG_8156B) {
2002 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0200);
2003 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0400);
2004 }
2005
2006 /* Configure Rx FIFO threshold. */
2007 if (sc->sc_flags & URE_FLAG_8153B) {
2008 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, URE_RXFIFO_THR1_NORMAL);
2009 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, URE_RXFIFO_THR2_NORMAL);
2010 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, URE_RXFIFO_THR3_NORMAL);
2011 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_B);
2012 } else {
2013 ure_write_2(sc, 0xc0a2, URE_MCU_TYPE_PLA,
2014 (ure_read_2(sc, 0xc0a2, URE_MCU_TYPE_PLA) & ~0xfff) | 0x08);
2015 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 0x00600400);
2016 }
2017
2018 /* Configure Tx FIFO threshold. */
2019 if (sc->sc_flags & URE_FLAG_8153B) {
2020 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2);
2021 } else if (sc->sc_flags & URE_FLAG_8156) {
2022 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2);
2023 URE_SETBIT_2(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x0002);
2024 } else if (sc->sc_flags & URE_FLAG_8156B) {
2025 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 0x0008);
2026 ure_write_2(sc, 0xe61a, URE_MCU_TYPE_PLA,
2027 (URE_FRAMELEN(val) + 0x100) / 16 );
2028 }
2029
2030 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN);
2031
2032 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
2033 URE_CLRBIT_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0x300);
2034
2035 ure_enable_aldps(sc, true);
2036
2037 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
2038 /* Enable U2P3 */
2039 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
2040 }
2041
2042 /* Enable U1U2 */
2043 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER)
2044 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
2045 }
2046
2047 static void
ure_stop(struct usb_ether * ue)2048 ure_stop(struct usb_ether *ue)
2049 {
2050 struct ure_softc *sc = uether_getsc(ue);
2051 if_t ifp = uether_getifp(ue);
2052
2053 URE_LOCK_ASSERT(sc, MA_OWNED);
2054
2055 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2056 sc->sc_flags &= ~URE_FLAG_LINK;
2057 sc->sc_rxstarted = 0;
2058
2059 /*
2060 * stop all the transfers, if not already stopped:
2061 */
2062 for (int i = 0; i < URE_MAX_RX; i++)
2063 usbd_transfer_stop(sc->sc_rx_xfer[i]);
2064 for (int i = 0; i < URE_MAX_TX; i++)
2065 usbd_transfer_stop(sc->sc_tx_xfer[i]);
2066 }
2067
2068 static void
ure_disable_teredo(struct ure_softc * sc)2069 ure_disable_teredo(struct ure_softc *sc)
2070 {
2071
2072 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
2073 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff);
2074 else {
2075 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
2076 (URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
2077 }
2078 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE);
2079 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
2080 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
2081 }
2082
2083 static void
ure_enable_aldps(struct ure_softc * sc,bool enable)2084 ure_enable_aldps(struct ure_softc *sc, bool enable)
2085 {
2086 int i;
2087
2088 if (enable) {
2089 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
2090 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS);
2091 } else {
2092 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
2093 URE_DIS_SDSAVE);
2094 for (i = 0; i < 20; i++) {
2095 uether_pause(&sc->sc_ue, hz / 1000);
2096 if (ure_ocp_reg_read(sc, 0xe000) & 0x0100)
2097 break;
2098 }
2099 }
2100 }
2101
2102 static uint16_t
ure_phy_status(struct ure_softc * sc,uint16_t desired)2103 ure_phy_status(struct ure_softc *sc, uint16_t desired)
2104 {
2105 uint16_t val;
2106 int i;
2107
2108 for (i = 0; i < URE_TIMEOUT; i++) {
2109 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
2110 URE_PHY_STAT_MASK;
2111 if (desired) {
2112 if (val == desired)
2113 break;
2114 } else {
2115 if (val == URE_PHY_STAT_LAN_ON ||
2116 val == URE_PHY_STAT_PWRDN ||
2117 val == URE_PHY_STAT_EXT_INIT)
2118 break;
2119 }
2120 uether_pause(&sc->sc_ue, hz / 100);
2121 }
2122 if (i == URE_TIMEOUT)
2123 device_printf(sc->sc_ue.ue_dev,
2124 "timeout waiting for phy to stabilize\n");
2125
2126 return (val);
2127 }
2128
2129 static void
ure_rtl8152_nic_reset(struct ure_softc * sc)2130 ure_rtl8152_nic_reset(struct ure_softc *sc)
2131 {
2132 uint32_t rx_fifo1, rx_fifo2;
2133 int i;
2134
2135 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
2136
2137 ure_disable_teredo(sc);
2138
2139 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8152_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
2140 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
2141
2142 ure_reset(sc);
2143
2144 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
2145
2146 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
2147
2148 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
2149 for (i = 0; i < URE_TIMEOUT; i++) {
2150 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
2151 URE_LINK_LIST_READY)
2152 break;
2153 uether_pause(&sc->sc_ue, hz / 100);
2154 }
2155 if (i == URE_TIMEOUT)
2156 device_printf(sc->sc_ue.ue_dev,
2157 "timeout waiting for OOB control\n");
2158 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL);
2159 for (i = 0; i < URE_TIMEOUT; i++) {
2160 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
2161 URE_LINK_LIST_READY)
2162 break;
2163 uether_pause(&sc->sc_ue, hz / 100);
2164 }
2165 if (i == URE_TIMEOUT)
2166 device_printf(sc->sc_ue.ue_dev,
2167 "timeout waiting for OOB control\n");
2168
2169 URE_CLRBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, URE_CPCR_RX_VLAN);
2170
2171 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO);
2172
2173 /* Configure Rx FIFO threshold. */
2174 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
2175 URE_RXFIFO_THR1_NORMAL);
2176 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
2177 rx_fifo1 = URE_RXFIFO_THR2_FULL;
2178 rx_fifo2 = URE_RXFIFO_THR3_FULL;
2179 } else {
2180 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
2181 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
2182 }
2183 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
2184 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
2185
2186 /* Configure Tx FIFO threshold. */
2187 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
2188 URE_TXFIFO_THR_NORMAL);
2189 }
2190
2191 /*
2192 * Update mbuf for rx checksum from hardware
2193 */
2194 static void
ure_rxcsum(int capenb,struct ure_rxpkt * rp,struct mbuf * m)2195 ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m)
2196 {
2197 uint32_t csum, misc;
2198
2199 m->m_pkthdr.csum_flags = 0;
2200
2201 csum = le32toh(rp->ure_csum);
2202 misc = le32toh(rp->ure_misc);
2203
2204 if ((capenb & IFCAP_RXCSUM) == 0 &&
2205 (csum & URE_RXPKT_IPV4_CS) != 0)
2206 return;
2207 if ((capenb & IFCAP_RXCSUM_IPV6) == 0 &&
2208 (csum & URE_RXPKT_IPV6_CS) != 0)
2209 return;
2210
2211 if ((csum & URE_RXPKT_IPV4_CS) != 0) {
2212 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2213 if (__predict_true((misc & URE_RXPKT_IP_F) == 0))
2214 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2215 }
2216 if (__predict_true(
2217 ((rp->ure_csum & URE_RXPKT_TCP_CS) != 0 &&
2218 (misc & URE_RXPKT_TCP_F) == 0) ||
2219 ((rp->ure_csum & URE_RXPKT_UDP_CS) != 0 &&
2220 (misc & URE_RXPKT_UDP_F) == 0))) {
2221 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2222 m->m_pkthdr.csum_data = 0xFFFF;
2223 }
2224 }
2225
2226 /*
2227 * If the L4 checksum offset is larger than 0x7ff (2047), return failure.
2228 * We currently restrict MTU such that it can't happen, and even if we
2229 * did have a large enough MTU, only a very specially crafted IPv6 packet
2230 * with MANY headers could possibly come close.
2231 *
2232 * Returns 0 for success, and 1 if the packet cannot be checksummed and
2233 * should be dropped.
2234 */
2235 static int
ure_txcsum(struct mbuf * m,int caps,uint32_t * regout)2236 ure_txcsum(struct mbuf *m, int caps, uint32_t *regout)
2237 {
2238 struct ip ip;
2239 struct ether_header *eh;
2240 int flags;
2241 uint32_t reg;
2242 int l3off, l4off;
2243 uint16_t type;
2244
2245 *regout = 0;
2246 flags = m->m_pkthdr.csum_flags;
2247 if (flags == 0)
2248 return (0);
2249
2250 if (__predict_true(m->m_len >= (int)sizeof(*eh))) {
2251 eh = mtod(m, struct ether_header *);
2252 type = eh->ether_type;
2253 } else
2254 m_copydata(m, offsetof(struct ether_header, ether_type),
2255 sizeof(type), (caddr_t)&type);
2256
2257 switch (type = htons(type)) {
2258 case ETHERTYPE_IP:
2259 case ETHERTYPE_IPV6:
2260 l3off = ETHER_HDR_LEN;
2261 break;
2262 case ETHERTYPE_VLAN:
2263 /* XXX - what about QinQ? */
2264 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2265 break;
2266 default:
2267 return (0);
2268 }
2269
2270 reg = 0;
2271
2272 if (flags & CSUM_IP)
2273 reg |= URE_TXPKT_IPV4_CS;
2274
2275 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) {
2276 m_copydata(m, l3off, sizeof ip, (caddr_t)&ip);
2277 l4off = l3off + (ip.ip_hl << 2);
2278 if (__predict_false(l4off > URE_L4_OFFSET_MAX))
2279 return (1);
2280
2281 reg |= URE_TXPKT_IPV4_CS;
2282 if (flags & CSUM_IP_TCP)
2283 reg |= URE_TXPKT_TCP_CS;
2284 else if (flags & CSUM_IP_UDP)
2285 reg |= URE_TXPKT_UDP_CS;
2286 reg |= l4off << URE_L4_OFFSET_SHIFT;
2287 }
2288 #ifdef INET6
2289 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) {
2290 l4off = ip6_lasthdr(m, l3off, IPPROTO_IPV6, NULL);
2291 if (__predict_false(l4off < 0))
2292 return (1);
2293 if (__predict_false(l4off > URE_L4_OFFSET_MAX))
2294 return (1);
2295
2296 reg |= URE_TXPKT_IPV6_CS;
2297 if (flags & CSUM_IP6_TCP)
2298 reg |= URE_TXPKT_TCP_CS;
2299 else if (flags & CSUM_IP6_UDP)
2300 reg |= URE_TXPKT_UDP_CS;
2301 reg |= l4off << URE_L4_OFFSET_SHIFT;
2302 }
2303 #endif
2304 *regout = reg;
2305 return 0;
2306 }
2307