1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation.
3 */
4
5 #include "main.h"
6 #include "reg.h"
7 #include "bf.h"
8 #include "debug.h"
9
rtw_bf_disassoc(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf)10 void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
11 struct ieee80211_bss_conf *bss_conf)
12 {
13 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
14 struct rtw_bfee *bfee = &rtwvif->bfee;
15 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
16
17 if (bfee->role == RTW_BFEE_NONE)
18 return;
19
20 if (bfee->role == RTW_BFEE_MU)
21 bfinfo->bfer_mu_cnt--;
22 else if (bfee->role == RTW_BFEE_SU)
23 bfinfo->bfer_su_cnt--;
24
25 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, false);
26
27 bfee->role = RTW_BFEE_NONE;
28 }
29
rtw_bf_assoc(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf)30 void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
31 struct ieee80211_bss_conf *bss_conf)
32 {
33 const struct rtw_chip_info *chip = rtwdev->chip;
34 struct ieee80211_hw *hw = rtwdev->hw;
35 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
36 struct rtw_bfee *bfee = &rtwvif->bfee;
37 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
38 struct ieee80211_sta *sta;
39 struct ieee80211_sta_vht_cap *vht_cap;
40 struct ieee80211_sta_vht_cap *ic_vht_cap;
41 const u8 *bssid = bss_conf->bssid;
42 u32 sound_dim;
43 u8 i;
44
45 if (!(chip->band & RTW_BAND_5G))
46 return;
47
48 rcu_read_lock();
49
50 sta = ieee80211_find_sta(vif, bssid);
51 if (!sta) {
52 rcu_read_unlock();
53
54 #if defined(__linux__)
55 rtw_warn(rtwdev, "failed to find station entry for bss %pM\n",
56 bssid);
57 #elif defined(__FreeBSD__)
58 rtw_warn(rtwdev, "failed to find station entry for bss %6D\n",
59 bssid, ":");
60 #endif
61 return;
62 }
63
64 ic_vht_cap = &hw->wiphy->bands[NL80211_BAND_5GHZ]->vht_cap;
65 vht_cap = &sta->deflink.vht_cap;
66
67 rcu_read_unlock();
68
69 if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE) &&
70 (vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE)) {
71 if (bfinfo->bfer_mu_cnt >= chip->bfer_mu_max_num) {
72 rtw_dbg(rtwdev, RTW_DBG_BF, "mu bfer number over limit\n");
73 return;
74 }
75
76 ether_addr_copy(bfee->mac_addr, bssid);
77 bfee->role = RTW_BFEE_MU;
78 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
79 bfee->aid = vif->cfg.aid;
80 bfinfo->bfer_mu_cnt++;
81
82 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
83 } else if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE) &&
84 (vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
85 if (bfinfo->bfer_su_cnt >= chip->bfer_su_max_num) {
86 rtw_dbg(rtwdev, RTW_DBG_BF, "su bfer number over limit\n");
87 return;
88 }
89
90 sound_dim = vht_cap->cap &
91 IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK;
92 sound_dim >>= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT;
93
94 ether_addr_copy(bfee->mac_addr, bssid);
95 bfee->role = RTW_BFEE_SU;
96 bfee->sound_dim = (u8)sound_dim;
97 bfee->g_id = 0;
98 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
99 bfinfo->bfer_su_cnt++;
100 for (i = 0; i < chip->bfer_su_max_num; i++) {
101 if (!test_bit(i, bfinfo->bfer_su_reg_maping)) {
102 set_bit(i, bfinfo->bfer_su_reg_maping);
103 bfee->su_reg_index = i;
104 break;
105 }
106 }
107
108 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
109 }
110 }
111
rtw_bf_init_bfer_entry_mu(struct rtw_dev * rtwdev,struct mu_bfer_init_para * param)112 void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev,
113 struct mu_bfer_init_para *param)
114 {
115 u16 mu_bf_ctl = 0;
116 u8 *addr = param->bfer_address;
117 int i;
118
119 for (i = 0; i < ETH_ALEN; i++)
120 rtw_write8(rtwdev, REG_ASSOCIATED_BFMER0_INFO + i, addr[i]);
121 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
122 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
123
124 mu_bf_ctl = rtw_read16(rtwdev, REG_WMAC_MU_BF_CTL) & 0xC000;
125 mu_bf_ctl |= param->my_aid | (param->csi_length_sel << 12);
126 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, mu_bf_ctl);
127 }
128
rtw_bf_cfg_sounding(struct rtw_dev * rtwdev,struct rtw_vif * vif,enum rtw_trx_desc_rate rate)129 void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif,
130 enum rtw_trx_desc_rate rate)
131 {
132 u8 csi_rsc = CSI_RSC_FOLLOW_RX_PACKET_BW;
133 u32 psf_ctl = 0;
134
135 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
136 csi_rsc = CSI_RSC_PRIMARY_20M_BW;
137
138 psf_ctl = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
139 BIT_WMAC_USE_NDPARATE |
140 (csi_rsc << 13);
141
142 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
143 RTW_SND_CTRL_SOUNDING);
144 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, 0x26);
145 rtw_write8_clr(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF_REPORT_POLL);
146 rtw_write8_clr(rtwdev, REG_RXFLTMAP4, BIT_RXFLTMAP4_BF_REPORT_POLL);
147
148 if (vif->net_type == RTW_NET_AP_MODE)
149 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl | BIT(12));
150 else
151 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl & ~BIT(12));
152 }
153
rtw_bf_cfg_mu_bfee(struct rtw_dev * rtwdev,struct cfg_mumimo_para * param)154 void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param)
155 {
156 u8 mu_tbl_sel;
157 u8 mu_valid;
158
159 mu_valid = rtw_read8(rtwdev, REG_MU_TX_CTL) &
160 ~BIT_MASK_R_MU_TABLE_VALID;
161
162 rtw_write8(rtwdev, REG_MU_TX_CTL,
163 (mu_valid | BIT(0) | BIT(1)) & ~(BIT(7)));
164
165 mu_tbl_sel = rtw_read8(rtwdev, REG_MU_TX_CTL + 1) & 0xF8;
166
167 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel);
168 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[0]);
169 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]);
170 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
171 param->given_user_pos[1]);
172
173 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel | 1);
174 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[1]);
175 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]);
176 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
177 param->given_user_pos[3]);
178 }
179
rtw_bf_del_bfer_entry_mu(struct rtw_dev * rtwdev)180 void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev)
181 {
182 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
183 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
184 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
185 rtw_write8(rtwdev, REG_MU_TX_CTL, 0);
186 }
187
rtw_bf_del_sounding(struct rtw_dev * rtwdev)188 void rtw_bf_del_sounding(struct rtw_dev *rtwdev)
189 {
190 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 0);
191 }
192
rtw_bf_enable_bfee_su(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee)193 void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif,
194 struct rtw_bfee *bfee)
195 {
196 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
197 u8 nr_index = bfee->sound_dim;
198 u8 grouping = 0, codebookinfo = 1, coefficientsize = 3;
199 u32 addr_bfer_info, addr_csi_rpt, csi_param;
200 u8 i;
201
202 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an su bfee\n");
203
204 switch (bfee->su_reg_index) {
205 case 1:
206 addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO;
207 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20 + 2;
208 break;
209 case 0:
210 default:
211 addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO;
212 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20;
213 break;
214 }
215
216 /* Sounding protocol control */
217 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
218 RTW_SND_CTRL_SOUNDING);
219
220 /* MAC address/Partial AID of Beamformer */
221 for (i = 0; i < ETH_ALEN; i++)
222 rtw_write8(rtwdev, addr_bfer_info + i, bfee->mac_addr[i]);
223
224 csi_param = (u16)((coefficientsize << 10) |
225 (codebookinfo << 8) |
226 (grouping << 6) |
227 (nr_index << 3) |
228 nc_index);
229 rtw_write16(rtwdev, addr_csi_rpt, csi_param);
230
231 /* ndp rx standby timer */
232 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, RTW_NDP_RX_STANDBY_TIME);
233 }
234 EXPORT_SYMBOL(rtw_bf_enable_bfee_su);
235
236 /* nc index: 1 2T2R 0 1T1R
237 * nr index: 1 use Nsts 0 use reg setting
238 * codebookinfo: 1 802.11ac 3 802.11n
239 */
rtw_bf_enable_bfee_mu(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee)240 void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif,
241 struct rtw_bfee *bfee)
242 {
243 struct rtw_bf_info *bf_info = &rtwdev->bf_info;
244 struct mu_bfer_init_para param;
245 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
246 u8 nr_index = 1;
247 u8 grouping = 0, codebookinfo = 1, coefficientsize = 0;
248 u32 csi_param;
249
250 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an mu bfee\n");
251
252 csi_param = (u16)((coefficientsize << 10) |
253 (codebookinfo << 8) |
254 (grouping << 6) |
255 (nr_index << 3) |
256 nc_index);
257
258 rtw_dbg(rtwdev, RTW_DBG_BF, "nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n",
259 nc_index, nr_index, grouping, codebookinfo,
260 coefficientsize);
261
262 param.paid = bfee->p_aid;
263 param.csi_para = csi_param;
264 param.my_aid = bfee->aid & 0xfff;
265 param.csi_length_sel = HAL_CSI_SEG_4K;
266 ether_addr_copy(param.bfer_address, bfee->mac_addr);
267
268 rtw_bf_init_bfer_entry_mu(rtwdev, ¶m);
269
270 bf_info->cur_csi_rpt_rate = DESC_RATE6M;
271 rtw_bf_cfg_sounding(rtwdev, vif, DESC_RATE6M);
272
273 /* accept action_no_ack */
274 rtw_write16_set(rtwdev, REG_RXFLTMAP0, BIT_RXFLTMAP0_ACTIONNOACK);
275
276 /* accept NDPA and BF report poll */
277 rtw_write16_set(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF);
278 }
279 EXPORT_SYMBOL(rtw_bf_enable_bfee_mu);
280
rtw_bf_remove_bfee_su(struct rtw_dev * rtwdev,struct rtw_bfee * bfee)281 void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev,
282 struct rtw_bfee *bfee)
283 {
284 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
285
286 rtw_dbg(rtwdev, RTW_DBG_BF, "remove as a su bfee\n");
287 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
288 RTW_SND_CTRL_REMOVE);
289
290 switch (bfee->su_reg_index) {
291 case 0:
292 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
293 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
294 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, 0);
295 break;
296 case 1:
297 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER1_INFO, 0);
298 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER1_INFO + 4, 0);
299 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20 + 2, 0);
300 break;
301 }
302
303 clear_bit(bfee->su_reg_index, bfinfo->bfer_su_reg_maping);
304 bfee->su_reg_index = 0xFF;
305 }
306 EXPORT_SYMBOL(rtw_bf_remove_bfee_su);
307
rtw_bf_remove_bfee_mu(struct rtw_dev * rtwdev,struct rtw_bfee * bfee)308 void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev,
309 struct rtw_bfee *bfee)
310 {
311 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
312
313 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
314 RTW_SND_CTRL_REMOVE);
315
316 rtw_bf_del_bfer_entry_mu(rtwdev);
317
318 if (bfinfo->bfer_su_cnt == 0 && bfinfo->bfer_mu_cnt == 0)
319 rtw_bf_del_sounding(rtwdev);
320 }
321 EXPORT_SYMBOL(rtw_bf_remove_bfee_mu);
322
rtw_bf_set_gid_table(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * conf)323 void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
324 struct ieee80211_bss_conf *conf)
325 {
326 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
327 struct rtw_bfee *bfee = &rtwvif->bfee;
328 struct cfg_mumimo_para param;
329
330 if (bfee->role != RTW_BFEE_MU) {
331 rtw_dbg(rtwdev, RTW_DBG_BF, "this vif is not mu bfee\n");
332 return;
333 }
334
335 param.grouping_bitmap = 0;
336 param.mu_tx_en = 0;
337 memset(param.sounding_sts, 0, 6);
338 memcpy(param.given_gid_tab, conf->mu_group.membership, 8);
339 memcpy(param.given_user_pos, conf->mu_group.position, 16);
340 rtw_dbg(rtwdev, RTW_DBG_BF, "STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
341 param.given_gid_tab[0], param.given_user_pos[0],
342 param.given_user_pos[1]);
343
344 rtw_dbg(rtwdev, RTW_DBG_BF, "STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
345 param.given_gid_tab[1], param.given_user_pos[2],
346 param.given_user_pos[3]);
347
348 rtw_bf_cfg_mu_bfee(rtwdev, ¶m);
349 }
350 EXPORT_SYMBOL(rtw_bf_set_gid_table);
351
rtw_bf_phy_init(struct rtw_dev * rtwdev)352 void rtw_bf_phy_init(struct rtw_dev *rtwdev)
353 {
354 u8 tmp8;
355 u32 tmp32;
356 u8 retry_limit = 0xA;
357 u8 ndpa_rate = 0x10;
358 u8 ack_policy = 3;
359
360 tmp32 = rtw_read32(rtwdev, REG_MU_TX_CTL);
361 /* Enable P1 aggr new packet according to P0 transfer time */
362 tmp32 |= BIT_MU_P1_WAIT_STATE_EN;
363 /* MU Retry Limit */
364 tmp32 &= ~BIT_MASK_R_MU_RL;
365 tmp32 |= (retry_limit << BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL;
366 /* Disable Tx MU-MIMO until sounding done */
367 tmp32 &= ~BIT_EN_MU_MIMO;
368 /* Clear validity of MU STAs */
369 tmp32 &= ~BIT_MASK_R_MU_TABLE_VALID;
370 rtw_write32(rtwdev, REG_MU_TX_CTL, tmp32);
371
372 /* MU-MIMO Option as default value */
373 tmp8 = ack_policy << BIT_SHIFT_WMAC_TXMU_ACKPOLICY;
374 tmp8 |= BIT_WMAC_TXMU_ACKPOLICY_EN;
375 rtw_write8(rtwdev, REG_WMAC_MU_BF_OPTION, tmp8);
376
377 /* MU-MIMO Control as default value */
378 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
379 /* Set MU NDPA rate & BW source */
380 rtw_write32_set(rtwdev, REG_TXBF_CTRL, BIT_USE_NDPA_PARAMETER);
381 /* Set NDPA Rate */
382 rtw_write8(rtwdev, REG_NDPA_OPT_CTRL, ndpa_rate);
383
384 rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE,
385 DESC_RATE6M);
386 }
387 EXPORT_SYMBOL(rtw_bf_phy_init);
388
rtw_bf_cfg_csi_rate(struct rtw_dev * rtwdev,u8 rssi,u8 cur_rate,u8 fixrate_en,u8 * new_rate)389 void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
390 u8 fixrate_en, u8 *new_rate)
391 {
392 u32 csi_cfg;
393 u16 cur_rrsr;
394
395 csi_cfg = rtw_read32(rtwdev, REG_BBPSF_CTRL) & ~BIT_MASK_CSI_RATE;
396 cur_rrsr = rtw_read16(rtwdev, REG_RRSR);
397
398 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
399 csi_cfg |= BIT_CSI_FORCE_RATE;
400
401 if (rssi >= 40) {
402 if (cur_rate != DESC_RATE54M) {
403 cur_rrsr |= BIT(DESC_RATE54M);
404 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
405 BIT_SHIFT_CSI_RATE;
406 rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
407 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
408 }
409 *new_rate = DESC_RATE54M;
410 } else {
411 if (cur_rate != DESC_RATE24M) {
412 cur_rrsr &= ~BIT(DESC_RATE54M);
413 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
414 BIT_SHIFT_CSI_RATE;
415 rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
416 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
417 }
418 *new_rate = DESC_RATE24M;
419 }
420 }
421 EXPORT_SYMBOL(rtw_bf_cfg_csi_rate);
422