1.\" Copyright (c) 2023 The FreeBSD Foundation 2. 3.\" This documentation was written by Robert Clausecker <fuz@FreeBSD.org> 4.\" under sponsorship from the FreeBSD Foundation. 5. 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14. 15.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ''AS IS'' AND 16.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25.\" SUCH DAMAGE 26. 27.Dd October 21, 2025 28.Dt SIMD 7 29.Os 30.Sh NAME 31.Nm simd 32.Nd SIMD enhancements 33. 34.Sh DESCRIPTION 35On some architectures, the 36.Fx 37.Em libc 38provides enhanced implementations of commonly used functions, replacing 39the architecture-independent implementations used otherwise. 40Depending on architecture and function, an enhanced 41implementation of a function may either always be used or the 42.Em libc 43detects at runtime which SIMD instruction set extensions are 44supported and picks the most suitable implementation automatically. 45On 46.Cm amd64 , 47the environment variable 48.Ev ARCHLEVEL 49can be used to override this mechanism. 50.Pp 51Enhanced functions are present for the following architectures: 52.Bl -column FUNCTION_________ aarch64_ arm_ amd64_ i386_ ppc64_ -offset indent 53.It Em FUNCTION Ta Em AARCH64 Ta Em ARM Ta Em AMD64 Ta Em I386 Ta Em PPC64 Ta Em RISC-V 54.It bcmp Ta A Ta Ta S1 Ta S 55.It bcopy Ta A Ta S Ta S Ta S Ta SV Ta S 56.It bzero Ta A Ta S Ta S Ta S Ta Ta S 57.It div Ta Ta Ta S Ta S 58.It index Ta A Ta Ta S1 Ta Ta S 59.It ldiv Ta Ta Ta S Ta S 60.It lldiv Ta Ta Ta S 61.It memchr Ta A Ta Ta S1 Ta Ta Ta S 62.It memcmp Ta A Ta S Ta S1 Ta S 63.It memccpy Ta A Ta Ta S1 64.It memcpy Ta AM Ta S Ta S Ta S Ta SV Ta S 65.It memmove Ta AM Ta S Ta S Ta S Ta SV 66.It memrchr Ta A Ta Ta S1 67.It memset Ta AM Ta S Ta S Ta S Ta Ta S 68.It rindex Ta A Ta Ta S1 Ta S Ta Ta S 69.It stpcpy Ta A Ta Ta S1 70.It stpncpy Ta Ta Ta S1 71.It strcat Ta A Ta Ta S1 Ta S 72.It strchr Ta A Ta Ta S1 Ta S Ta Ta S 73.It strchrnul Ta A Ta Ta S1 Ta Ta Ta S 74.It strcmp Ta A Ta S Ta S1 Ta S 75.It strcpy Ta A Ta Ta S1 Ta S Ta S2 76.It strcspn Ta S Ta Ta S2 77.It strlcat Ta A Ta Ta S1 78.It strlcpy Ta A Ta Ta S1 79.It strlen Ta A Ta S Ta S1 Ta Ta Ta S 80.It strncat Ta A Ta Ta S1 81.It strncmp Ta A Ta S Ta S1 Ta S 82.It strncpy Ta Ta Ta S1 Ta Ta S2 83.It strnlen Ta A Ta Ta S1 Ta Ta Ta S 84.It strrchr Ta A Ta Ta S1 Ta S Ta Ta S 85.It strpbrk Ta S Ta Ta S2 86.It strsep Ta S Ta Ta S2 87.It strspn Ta S Ta Ta S2 88.It swab Ta Ta Ta Ta S 89.It timingsafe_bcmp Ta A Ta Ta S1 90.It timingsafe_memcmp Ta S Ta Ta S 91.It wcschr Ta Ta Ta Ta S 92.It wcscmp Ta Ta Ta Ta S 93.It wcslen Ta Ta Ta Ta S 94.It wmemchr Ta Ta Ta Ta S 95.El 96.Pp 97.Sy S Ns :\ scalar (non-SIMD), 98.Sy 1 Ns :\ amd64 baseline, 99.Sy 2 Ns :\ x86-64-v2 100or PowerPC\ 2.05, 101.Sy 3 Ns :\ x86-64-v3, 102.Sy 4 Ns :\ x86-64-v4, 103.Sy V Ns :\ PowerPC\ VSX, 104.Sy A Ns :\ Arm\ ASIMD (NEON), 105.Sy M Ns :\ Arm\ MOPS. 106. 107.Sh ENVIRONMENT 108.Bl -tag 109.It Ev ARCHLEVEL 110On 111.Em amd64 , 112controls the level of SIMD enhancements used. 113If this variable is set to an architecture level from the list below 114and that architecture level is supported by the processor, SIMD 115enhancements up to 116.Ev ARCHLEVEL 117are used. 118If 119.Ev ARCHLEVEL 120is unset, not recognised, or not supported by the processor, the highest 121level of SIMD enhancements supported by the processor is used. 122.Pp 123A suffix beginning with 124.Sq ":" 125or 126.Sq "+" 127in 128.Ev ARCHLEVEL 129is ignored and may be used for future extensions. 130The architecture level can be prefixed with a 131.Sq "!" 132character to force use of the requested architecture level, even if the 133processor does not advertise that it is supported. 134This usually causes applications to crash and should only be used for 135testing purposes or if architecture level detection yields incorrect 136results. 137.Pp 138The architecture levels follow the AMD64 SysV ABI supplement: 139.Bl -tag -width x86-64-v2 140.It Cm scalar 141scalar enhancements only (no SIMD) 142.It Cm baseline 143cmov, cx8, x87 FPU, fxsr, MMX, osfxsr, SSE, SSE2 144.It Cm x86-64-v2 145cx16, lahf/sahf, popcnt, SSE3, SSSE3, SSE4.1, SSE4.2 146.It Cm x86-64-v3 147AVX, AVX2, BMI1, BMI2, F16C, FMA, lzcnt, movbe, osxsave 148.It Cm x86-64-v4 149AVX-512F/BW/CD/DQ/VL 150.El 151.El 152. 153.Sh DIAGNOSTICS 154.Bl -diag 155.It "Illegal Instruction" 156Printed by 157.Xr sh 1 158if a command is terminated through delivery of a 159.Dv SIGILL 160signal, see 161.Xr signal 3 . 162.Pp 163Use of an unsupported architecture level was forced by setting 164.Ev ARCHLEVEL 165to a string beginning with a 166.Sq "!" 167character, causing a process to crash due to use of an unsupported 168instruction. 169Unset 170.Ev ARCHLEVEL , 171remove the 172.Sq "!" 173prefix or select a supported architecture level. 174.Pp 175Message may also appear for unrelated reasons. 176.El 177. 178.Sh SEE ALSO 179.Xr string 3 , 180.Xr arch 7 181.Rs 182.%A H. J. Lu 183.%A Michael Matz 184.%A Milind Girkar 185.%A Jan Hubi\[u010D]ka \" \(vc 186.%A Andreas Jaeger 187.%A Mark Mitchell 188.%B System V Application Binary Interface 189.%D May 23, 2023 190.%T AMD64 Architecture Processor Supplement 191.%O Version 1.0 192.Re 193. 194.Sh HISTORY 195Architecture-specific enhanced 196.Em libc 197functions were added starting 198with 199.Fx 2.0 200for 201.Cm i386 , 202.Fx 6.0 203for 204.Cm arm , 205.Fx 6.1 206for 207.Cm amd64 , 208.Fx 11.0 209for 210.Cm aarch64 , 211.Fx 12.0 212for 213.Cm powerpc64 , 214and 215.Fx 16.0 216for 217.Cm riscv64 . 218SIMD-enhanced functions were first added with 219.Fx 13.0 220for 221.Cm powerpc64 222and with 223.Fx 14.1 224for 225.Cm amd64 . 226.Pp 227A 228.Nm 229manual page appeared in 230.Fx 14.1 . 231. 232.Sh AUTHOR 233.An Robert Clausecker Aq Mt fuz@FreeBSD.org 234. 235.Sh CAVEATS 236Other parts of 237.Fx 238such as cryptographic routines in the kernel or in 239OpenSSL may also use SIMD enhancements. 240These enhancements are not subject to the 241.Ev ARCHLEVEL 242variable and may have their own configuration 243mechanism. 244. 245.Sh BUGS 246Use of SIMD enhancements cannot be configured on powerpc64. 247