1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2009, 2011 Stefan Weil 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* 26 * This code implements a TCG which does not generate machine code for some 27 * real target machine but which generates virtual machine code for an 28 * interpreter. Interpreted pseudo code is slow, but it works on any host. 29 * 30 * Some remarks might help in understanding the code: 31 * 32 * "target" or "TCG target" is the machine which runs the generated code. 33 * This is different to the usual meaning in QEMU where "target" is the 34 * emulated machine. So normally QEMU host is identical to TCG target. 35 * Here the TCG target is a virtual machine, but this virtual machine must 36 * use the same word size like the real machine. 37 * Therefore, we need both 32 and 64 bit virtual machines (interpreter). 38 */ 39 40 #ifndef TCG_TARGET_H 41 #define TCG_TARGET_H 42 43 #define TCG_TARGET_INTERPRETER 1 44 #define TCG_TARGET_INSN_UNIT_SIZE 4 45 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) 46 47 /* Number of registers available. */ 48 #define TCG_TARGET_NB_REGS 16 49 50 /* List of registers which are used by TCG. */ 51 typedef enum { 52 TCG_REG_R0 = 0, 53 TCG_REG_R1, 54 TCG_REG_R2, 55 TCG_REG_R3, 56 TCG_REG_R4, 57 TCG_REG_R5, 58 TCG_REG_R6, 59 TCG_REG_R7, 60 TCG_REG_R8, 61 TCG_REG_R9, 62 TCG_REG_R10, 63 TCG_REG_R11, 64 TCG_REG_R12, 65 TCG_REG_R13, 66 TCG_REG_R14, 67 TCG_REG_R15, 68 69 TCG_REG_TMP = TCG_REG_R13, 70 TCG_AREG0 = TCG_REG_R14, 71 TCG_REG_CALL_STACK = TCG_REG_R15, 72 } TCGReg; 73 74 #define HAVE_TCG_QEMU_TB_EXEC 75 76 #endif /* TCG_TARGET_H */ 77