xref: /qemu/tcg/sparc64/tcg-target.h (revision 6b8abd244b9355bc840bc14182aae9043f86f2f6)
1 /*
2  * Tiny Code Generator for QEMU
3  *
4  * Copyright (c) 2008 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #ifndef SPARC_TCG_TARGET_H
26 #define SPARC_TCG_TARGET_H
27 
28 #define TCG_TARGET_INSN_UNIT_SIZE 4
29 #define TCG_TARGET_NB_REGS 32
30 #define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
31 
32 typedef enum {
33     TCG_REG_G0 = 0,
34     TCG_REG_G1,
35     TCG_REG_G2,
36     TCG_REG_G3,
37     TCG_REG_G4,
38     TCG_REG_G5,
39     TCG_REG_G6,
40     TCG_REG_G7,
41     TCG_REG_O0,
42     TCG_REG_O1,
43     TCG_REG_O2,
44     TCG_REG_O3,
45     TCG_REG_O4,
46     TCG_REG_O5,
47     TCG_REG_O6,
48     TCG_REG_O7,
49     TCG_REG_L0,
50     TCG_REG_L1,
51     TCG_REG_L2,
52     TCG_REG_L3,
53     TCG_REG_L4,
54     TCG_REG_L5,
55     TCG_REG_L6,
56     TCG_REG_L7,
57     TCG_REG_I0,
58     TCG_REG_I1,
59     TCG_REG_I2,
60     TCG_REG_I3,
61     TCG_REG_I4,
62     TCG_REG_I5,
63     TCG_REG_I6,
64     TCG_REG_I7,
65 } TCGReg;
66 
67 #define TCG_AREG0     TCG_REG_I0
68 #define TCG_REG_ZERO  TCG_REG_G0
69 
70 #endif
71