1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2018 SiFive, Inc 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 /* optional instructions */ 13 #define TCG_TARGET_HAS_negsetcond_i32 1 14 #define TCG_TARGET_HAS_div_i32 1 15 #define TCG_TARGET_HAS_rem_i32 1 16 #define TCG_TARGET_HAS_div2_i32 0 17 #define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB) 18 #define TCG_TARGET_HAS_extract2_i32 0 19 #define TCG_TARGET_HAS_add2_i32 1 20 #define TCG_TARGET_HAS_sub2_i32 1 21 #define TCG_TARGET_HAS_mulu2_i32 0 22 #define TCG_TARGET_HAS_muls2_i32 0 23 #define TCG_TARGET_HAS_muluh_i32 0 24 #define TCG_TARGET_HAS_mulsh_i32 0 25 #define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) 26 #define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) 27 #define TCG_TARGET_HAS_not_i32 1 28 #define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB) 29 #define TCG_TARGET_HAS_nand_i32 0 30 #define TCG_TARGET_HAS_nor_i32 0 31 #define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) 32 #define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) 33 #define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) 34 #define TCG_TARGET_HAS_qemu_st8_i32 0 35 36 #define TCG_TARGET_HAS_negsetcond_i64 1 37 #define TCG_TARGET_HAS_div_i64 1 38 #define TCG_TARGET_HAS_rem_i64 1 39 #define TCG_TARGET_HAS_div2_i64 0 40 #define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB) 41 #define TCG_TARGET_HAS_extract2_i64 0 42 #define TCG_TARGET_HAS_extr_i64_i32 1 43 #define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB) 44 #define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) 45 #define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) 46 #define TCG_TARGET_HAS_not_i64 1 47 #define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB) 48 #define TCG_TARGET_HAS_nand_i64 0 49 #define TCG_TARGET_HAS_nor_i64 0 50 #define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB) 51 #define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB) 52 #define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB) 53 #define TCG_TARGET_HAS_add2_i64 1 54 #define TCG_TARGET_HAS_sub2_i64 1 55 #define TCG_TARGET_HAS_mulu2_i64 0 56 #define TCG_TARGET_HAS_muls2_i64 0 57 #define TCG_TARGET_HAS_muluh_i64 1 58 #define TCG_TARGET_HAS_mulsh_i64 1 59 60 #define TCG_TARGET_HAS_qemu_ldst_i128 0 61 62 #define TCG_TARGET_HAS_tst 0 63 64 /* vector instructions */ 65 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_ZVE64X) 66 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_ZVE64X) 67 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_ZVE64X) 68 #define TCG_TARGET_HAS_andc_vec 0 69 #define TCG_TARGET_HAS_orc_vec 0 70 #define TCG_TARGET_HAS_nand_vec 0 71 #define TCG_TARGET_HAS_nor_vec 0 72 #define TCG_TARGET_HAS_eqv_vec 0 73 #define TCG_TARGET_HAS_not_vec 1 74 #define TCG_TARGET_HAS_neg_vec 1 75 #define TCG_TARGET_HAS_abs_vec 0 76 #define TCG_TARGET_HAS_roti_vec 1 77 #define TCG_TARGET_HAS_rots_vec 1 78 #define TCG_TARGET_HAS_rotv_vec 1 79 #define TCG_TARGET_HAS_shi_vec 1 80 #define TCG_TARGET_HAS_shs_vec 1 81 #define TCG_TARGET_HAS_shv_vec 1 82 #define TCG_TARGET_HAS_mul_vec 1 83 #define TCG_TARGET_HAS_sat_vec 1 84 #define TCG_TARGET_HAS_minmax_vec 1 85 #define TCG_TARGET_HAS_bitsel_vec 0 86 #define TCG_TARGET_HAS_cmpsel_vec 1 87 88 #define TCG_TARGET_HAS_tst_vec 0 89 90 static inline bool 91 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) 92 { 93 if (type == TCG_TYPE_I64 && ofs + len == 32) { 94 /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ 95 return ofs || (cpuinfo & CPUINFO_ZBA); 96 } 97 switch (len) { 98 case 1: 99 return (cpuinfo & CPUINFO_ZBS) && ofs != 0; 100 case 16: 101 return (cpuinfo & CPUINFO_ZBB) && ofs == 0; 102 } 103 return false; 104 } 105 #define TCG_TARGET_extract_valid tcg_target_extract_valid 106 107 static inline bool 108 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 109 { 110 if (type == TCG_TYPE_I64 && ofs + len == 32) { 111 return true; 112 } 113 return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16); 114 } 115 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 116 117 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 118 119 #endif 120