1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2018 SiFive, Inc 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 /* optional instructions */ 13 #define TCG_TARGET_HAS_qemu_st8_i32 0 14 15 #define TCG_TARGET_HAS_extr_i64_i32 1 16 #define TCG_TARGET_HAS_add2_i64 0 17 #define TCG_TARGET_HAS_sub2_i64 0 18 19 #define TCG_TARGET_HAS_qemu_ldst_i128 0 20 21 #define TCG_TARGET_HAS_tst 0 22 23 /* vector instructions */ 24 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_ZVE64X) 25 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_ZVE64X) 26 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_ZVE64X) 27 #define TCG_TARGET_HAS_andc_vec 0 28 #define TCG_TARGET_HAS_orc_vec 0 29 #define TCG_TARGET_HAS_nand_vec 0 30 #define TCG_TARGET_HAS_nor_vec 0 31 #define TCG_TARGET_HAS_eqv_vec 0 32 #define TCG_TARGET_HAS_not_vec 1 33 #define TCG_TARGET_HAS_neg_vec 1 34 #define TCG_TARGET_HAS_abs_vec 0 35 #define TCG_TARGET_HAS_roti_vec 1 36 #define TCG_TARGET_HAS_rots_vec 1 37 #define TCG_TARGET_HAS_rotv_vec 1 38 #define TCG_TARGET_HAS_shi_vec 1 39 #define TCG_TARGET_HAS_shs_vec 1 40 #define TCG_TARGET_HAS_shv_vec 1 41 #define TCG_TARGET_HAS_mul_vec 1 42 #define TCG_TARGET_HAS_sat_vec 1 43 #define TCG_TARGET_HAS_minmax_vec 1 44 #define TCG_TARGET_HAS_bitsel_vec 0 45 #define TCG_TARGET_HAS_cmpsel_vec 1 46 47 #define TCG_TARGET_HAS_tst_vec 0 48 49 static inline bool 50 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) 51 { 52 if (type == TCG_TYPE_I64 && ofs + len == 32) { 53 /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ 54 return ofs || (cpuinfo & CPUINFO_ZBA); 55 } 56 switch (len) { 57 case 1: 58 return (cpuinfo & CPUINFO_ZBS) && ofs != 0; 59 case 16: 60 return (cpuinfo & CPUINFO_ZBB) && ofs == 0; 61 } 62 return false; 63 } 64 #define TCG_TARGET_extract_valid tcg_target_extract_valid 65 66 static inline bool 67 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 68 { 69 if (type == TCG_TYPE_I64 && ofs + len == 32) { 70 return true; 71 } 72 return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16); 73 } 74 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 75 76 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 77 78 #endif 79