xref: /qemu/tcg/riscv/tcg-target-has.h (revision ee97eef290cde22c39b8715802bb3b0ca4555be3)

/* SPDX-License-Identifier: MIT */
/*
 * Define target-specific opcode support
 * Copyright (c) 2018 SiFive, Inc
 */

#ifndef TCG_TARGET_HAS_H
#define TCG_TARGET_HAS_H

#include "host/cpuinfo.h"

/* optional instructions */
#define TCG_TARGET_HAS_negsetcond_i32   1
#define TCG_TARGET_HAS_div_i32          1
#define TCG_TARGET_HAS_rem_i32          1
#define TCG_TARGET_HAS_div2_i32         0
#define TCG_TARGET_HAS_rot_i32          (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_extract2_i32     0
#define TCG_TARGET_HAS_add2_i32         1
#define TCG_TARGET_HAS_sub2_i32         1
#define TCG_TARGET_HAS_mulu2_i32        0
#define TCG_TARGET_HAS_muls2_i32        0
#define TCG_TARGET_HAS_muluh_i32        0
#define TCG_TARGET_HAS_mulsh_i32        0
#define TCG_TARGET_HAS_ext8s_i32        1
#define TCG_TARGET_HAS_ext16s_i32       1
#define TCG_TARGET_HAS_ext8u_i32        1
#define TCG_TARGET_HAS_ext16u_i32       1
#define TCG_TARGET_HAS_bswap16_i32      (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap32_i32      (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i32          1
#define TCG_TARGET_HAS_andc_i32         (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_orc_i32          (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_eqv_i32          (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_nand_i32         0
#define TCG_TARGET_HAS_nor_i32          0
#define TCG_TARGET_HAS_clz_i32          (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_ctz_i32          (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_ctpop_i32        (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_brcond2          1
#define TCG_TARGET_HAS_setcond2         1
#define TCG_TARGET_HAS_qemu_st8_i32     0

#define TCG_TARGET_HAS_negsetcond_i64   1
#define TCG_TARGET_HAS_div_i64          1
#define TCG_TARGET_HAS_rem_i64          1
#define TCG_TARGET_HAS_div2_i64         0
#define TCG_TARGET_HAS_rot_i64          (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_extract2_i64     0
#define TCG_TARGET_HAS_extr_i64_i32     1
#define TCG_TARGET_HAS_ext8s_i64        1
#define TCG_TARGET_HAS_ext16s_i64       1
#define TCG_TARGET_HAS_ext32s_i64       1
#define TCG_TARGET_HAS_ext8u_i64        1
#define TCG_TARGET_HAS_ext16u_i64       1
#define TCG_TARGET_HAS_ext32u_i64       1
#define TCG_TARGET_HAS_bswap16_i64      (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap32_i64      (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap64_i64      (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i64          1
#define TCG_TARGET_HAS_andc_i64         (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_orc_i64          (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_eqv_i64          (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_nand_i64         0
#define TCG_TARGET_HAS_nor_i64          0
#define TCG_TARGET_HAS_clz_i64          (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_ctz_i64          (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_ctpop_i64        (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_add2_i64         1
#define TCG_TARGET_HAS_sub2_i64         1
#define TCG_TARGET_HAS_mulu2_i64        0
#define TCG_TARGET_HAS_muls2_i64        0
#define TCG_TARGET_HAS_muluh_i64        1
#define TCG_TARGET_HAS_mulsh_i64        1

#define TCG_TARGET_HAS_qemu_ldst_i128   0

#define TCG_TARGET_HAS_tst              0

/* vector instructions */
#define TCG_TARGET_HAS_v64              (cpuinfo & CPUINFO_ZVE64X)
#define TCG_TARGET_HAS_v128             (cpuinfo & CPUINFO_ZVE64X)
#define TCG_TARGET_HAS_v256             (cpuinfo & CPUINFO_ZVE64X)
#define TCG_TARGET_HAS_andc_vec         0
#define TCG_TARGET_HAS_orc_vec          0
#define TCG_TARGET_HAS_nand_vec         0
#define TCG_TARGET_HAS_nor_vec          0
#define TCG_TARGET_HAS_eqv_vec          0
#define TCG_TARGET_HAS_not_vec          1
#define TCG_TARGET_HAS_neg_vec          1
#define TCG_TARGET_HAS_abs_vec          0
#define TCG_TARGET_HAS_roti_vec         1
#define TCG_TARGET_HAS_rots_vec         1
#define TCG_TARGET_HAS_rotv_vec         1
#define TCG_TARGET_HAS_shi_vec          1
#define TCG_TARGET_HAS_shs_vec          1
#define TCG_TARGET_HAS_shv_vec          1
#define TCG_TARGET_HAS_mul_vec          1
#define TCG_TARGET_HAS_sat_vec          1
#define TCG_TARGET_HAS_minmax_vec       1
#define TCG_TARGET_HAS_bitsel_vec       0
#define TCG_TARGET_HAS_cmpsel_vec       1

#define TCG_TARGET_HAS_tst_vec          0

static inline bool
tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
{
    if (type == TCG_TYPE_I64 && ofs + len == 32) {
        /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */
        return ofs || (cpuinfo & CPUINFO_ZBA);
    }
    switch (len) {
    case 1:
        return (cpuinfo & CPUINFO_ZBS) && ofs != 0;
    case 16:
        return (cpuinfo & CPUINFO_ZBB) && ofs == 0;
    }
    return false;
}
#define TCG_TARGET_extract_valid  tcg_target_extract_valid

static inline bool
tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
{
    if (type == TCG_TYPE_I64 && ofs + len == 32) {
        return true;
    }
    return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16);
}
#define TCG_TARGET_sextract_valid  tcg_target_sextract_valid

#define TCG_TARGET_deposit_valid(type, ofs, len)  0

#endif