1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2008 Fabrice Bellard 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 #define have_isa_2_06 (cpuinfo & CPUINFO_V2_06) 13 #define have_isa_2_07 (cpuinfo & CPUINFO_V2_07) 14 #define have_isa_3_00 (cpuinfo & CPUINFO_V3_0) 15 #define have_isa_3_10 (cpuinfo & CPUINFO_V3_1) 16 #define have_altivec (cpuinfo & CPUINFO_ALTIVEC) 17 #define have_vsx (cpuinfo & CPUINFO_VSX) 18 19 /* optional instructions */ 20 #define TCG_TARGET_HAS_div_i32 1 21 #define TCG_TARGET_HAS_rem_i32 have_isa_3_00 22 #define TCG_TARGET_HAS_rot_i32 1 23 #define TCG_TARGET_HAS_bswap16_i32 1 24 #define TCG_TARGET_HAS_bswap32_i32 1 25 #define TCG_TARGET_HAS_clz_i32 1 26 #define TCG_TARGET_HAS_ctz_i32 have_isa_3_00 27 #define TCG_TARGET_HAS_ctpop_i32 have_isa_2_06 28 #define TCG_TARGET_HAS_extract2_i32 0 29 #define TCG_TARGET_HAS_negsetcond_i32 1 30 #define TCG_TARGET_HAS_mulu2_i32 0 31 #define TCG_TARGET_HAS_muls2_i32 0 32 #define TCG_TARGET_HAS_qemu_st8_i32 0 33 34 #if TCG_TARGET_REG_BITS == 64 35 #define TCG_TARGET_HAS_add2_i32 0 36 #define TCG_TARGET_HAS_sub2_i32 0 37 #define TCG_TARGET_HAS_extr_i64_i32 0 38 #define TCG_TARGET_HAS_div_i64 1 39 #define TCG_TARGET_HAS_rem_i64 have_isa_3_00 40 #define TCG_TARGET_HAS_rot_i64 1 41 #define TCG_TARGET_HAS_bswap16_i64 1 42 #define TCG_TARGET_HAS_bswap32_i64 1 43 #define TCG_TARGET_HAS_bswap64_i64 1 44 #define TCG_TARGET_HAS_clz_i64 1 45 #define TCG_TARGET_HAS_ctz_i64 have_isa_3_00 46 #define TCG_TARGET_HAS_ctpop_i64 have_isa_2_06 47 #define TCG_TARGET_HAS_extract2_i64 0 48 #define TCG_TARGET_HAS_negsetcond_i64 1 49 #define TCG_TARGET_HAS_add2_i64 1 50 #define TCG_TARGET_HAS_sub2_i64 1 51 #define TCG_TARGET_HAS_mulu2_i64 0 52 #define TCG_TARGET_HAS_muls2_i64 0 53 #endif 54 55 #define TCG_TARGET_HAS_qemu_ldst_i128 \ 56 (TCG_TARGET_REG_BITS == 64 && have_isa_2_07) 57 58 #define TCG_TARGET_HAS_tst 1 59 60 /* 61 * While technically Altivec could support V64, it has no 64-bit store 62 * instruction and substituting two 32-bit stores makes the generated 63 * code quite large. 64 */ 65 #define TCG_TARGET_HAS_v64 have_vsx 66 #define TCG_TARGET_HAS_v128 have_altivec 67 #define TCG_TARGET_HAS_v256 0 68 69 #define TCG_TARGET_HAS_andc_vec 1 70 #define TCG_TARGET_HAS_orc_vec have_isa_2_07 71 #define TCG_TARGET_HAS_nand_vec have_isa_2_07 72 #define TCG_TARGET_HAS_nor_vec 1 73 #define TCG_TARGET_HAS_eqv_vec have_isa_2_07 74 #define TCG_TARGET_HAS_not_vec 1 75 #define TCG_TARGET_HAS_neg_vec have_isa_3_00 76 #define TCG_TARGET_HAS_abs_vec 0 77 #define TCG_TARGET_HAS_roti_vec 0 78 #define TCG_TARGET_HAS_rots_vec 0 79 #define TCG_TARGET_HAS_rotv_vec 1 80 #define TCG_TARGET_HAS_shi_vec 0 81 #define TCG_TARGET_HAS_shs_vec 0 82 #define TCG_TARGET_HAS_shv_vec 1 83 #define TCG_TARGET_HAS_mul_vec 1 84 #define TCG_TARGET_HAS_sat_vec 1 85 #define TCG_TARGET_HAS_minmax_vec 1 86 #define TCG_TARGET_HAS_bitsel_vec have_vsx 87 #define TCG_TARGET_HAS_cmpsel_vec 1 88 #define TCG_TARGET_HAS_tst_vec 0 89 90 #define TCG_TARGET_extract_valid(type, ofs, len) 1 91 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 92 93 static inline bool 94 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 95 { 96 if (type == TCG_TYPE_I64 && ofs + len == 32) { 97 return true; 98 } 99 return ofs == 0 && (len == 8 || len == 16); 100 } 101 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 102 103 #endif 104