1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2008 Fabrice Bellard 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 #define have_isa_2_06 (cpuinfo & CPUINFO_V2_06) 13 #define have_isa_2_07 (cpuinfo & CPUINFO_V2_07) 14 #define have_isa_3_00 (cpuinfo & CPUINFO_V3_0) 15 #define have_isa_3_10 (cpuinfo & CPUINFO_V3_1) 16 #define have_altivec (cpuinfo & CPUINFO_ALTIVEC) 17 #define have_vsx (cpuinfo & CPUINFO_VSX) 18 19 /* optional instructions automatically implemented */ 20 #define TCG_TARGET_HAS_ext8u_i32 0 /* andi */ 21 #define TCG_TARGET_HAS_ext16u_i32 0 22 23 /* optional instructions */ 24 #define TCG_TARGET_HAS_div_i32 1 25 #define TCG_TARGET_HAS_rem_i32 have_isa_3_00 26 #define TCG_TARGET_HAS_rot_i32 1 27 #define TCG_TARGET_HAS_ext8s_i32 1 28 #define TCG_TARGET_HAS_ext16s_i32 1 29 #define TCG_TARGET_HAS_bswap16_i32 1 30 #define TCG_TARGET_HAS_bswap32_i32 1 31 #define TCG_TARGET_HAS_not_i32 1 32 #define TCG_TARGET_HAS_andc_i32 1 33 #define TCG_TARGET_HAS_orc_i32 1 34 #define TCG_TARGET_HAS_eqv_i32 1 35 #define TCG_TARGET_HAS_nand_i32 1 36 #define TCG_TARGET_HAS_nor_i32 1 37 #define TCG_TARGET_HAS_clz_i32 1 38 #define TCG_TARGET_HAS_ctz_i32 have_isa_3_00 39 #define TCG_TARGET_HAS_ctpop_i32 have_isa_2_06 40 #define TCG_TARGET_HAS_extract2_i32 0 41 #define TCG_TARGET_HAS_negsetcond_i32 1 42 #define TCG_TARGET_HAS_mulu2_i32 0 43 #define TCG_TARGET_HAS_muls2_i32 0 44 #define TCG_TARGET_HAS_muluh_i32 1 45 #define TCG_TARGET_HAS_mulsh_i32 1 46 #define TCG_TARGET_HAS_qemu_st8_i32 0 47 48 #if TCG_TARGET_REG_BITS == 64 49 #define TCG_TARGET_HAS_add2_i32 0 50 #define TCG_TARGET_HAS_sub2_i32 0 51 #define TCG_TARGET_HAS_extr_i64_i32 0 52 #define TCG_TARGET_HAS_div_i64 1 53 #define TCG_TARGET_HAS_rem_i64 have_isa_3_00 54 #define TCG_TARGET_HAS_rot_i64 1 55 #define TCG_TARGET_HAS_ext8s_i64 1 56 #define TCG_TARGET_HAS_ext16s_i64 1 57 #define TCG_TARGET_HAS_ext32s_i64 1 58 #define TCG_TARGET_HAS_ext8u_i64 0 59 #define TCG_TARGET_HAS_ext16u_i64 0 60 #define TCG_TARGET_HAS_ext32u_i64 0 61 #define TCG_TARGET_HAS_bswap16_i64 1 62 #define TCG_TARGET_HAS_bswap32_i64 1 63 #define TCG_TARGET_HAS_bswap64_i64 1 64 #define TCG_TARGET_HAS_not_i64 1 65 #define TCG_TARGET_HAS_andc_i64 1 66 #define TCG_TARGET_HAS_orc_i64 1 67 #define TCG_TARGET_HAS_eqv_i64 1 68 #define TCG_TARGET_HAS_nand_i64 1 69 #define TCG_TARGET_HAS_nor_i64 1 70 #define TCG_TARGET_HAS_clz_i64 1 71 #define TCG_TARGET_HAS_ctz_i64 have_isa_3_00 72 #define TCG_TARGET_HAS_ctpop_i64 have_isa_2_06 73 #define TCG_TARGET_HAS_extract2_i64 0 74 #define TCG_TARGET_HAS_negsetcond_i64 1 75 #define TCG_TARGET_HAS_add2_i64 1 76 #define TCG_TARGET_HAS_sub2_i64 1 77 #define TCG_TARGET_HAS_mulu2_i64 0 78 #define TCG_TARGET_HAS_muls2_i64 0 79 #define TCG_TARGET_HAS_muluh_i64 1 80 #define TCG_TARGET_HAS_mulsh_i64 1 81 #endif 82 83 #define TCG_TARGET_HAS_qemu_ldst_i128 \ 84 (TCG_TARGET_REG_BITS == 64 && have_isa_2_07) 85 86 #define TCG_TARGET_HAS_tst 1 87 88 /* 89 * While technically Altivec could support V64, it has no 64-bit store 90 * instruction and substituting two 32-bit stores makes the generated 91 * code quite large. 92 */ 93 #define TCG_TARGET_HAS_v64 have_vsx 94 #define TCG_TARGET_HAS_v128 have_altivec 95 #define TCG_TARGET_HAS_v256 0 96 97 #define TCG_TARGET_HAS_andc_vec 1 98 #define TCG_TARGET_HAS_orc_vec have_isa_2_07 99 #define TCG_TARGET_HAS_nand_vec have_isa_2_07 100 #define TCG_TARGET_HAS_nor_vec 1 101 #define TCG_TARGET_HAS_eqv_vec have_isa_2_07 102 #define TCG_TARGET_HAS_not_vec 1 103 #define TCG_TARGET_HAS_neg_vec have_isa_3_00 104 #define TCG_TARGET_HAS_abs_vec 0 105 #define TCG_TARGET_HAS_roti_vec 0 106 #define TCG_TARGET_HAS_rots_vec 0 107 #define TCG_TARGET_HAS_rotv_vec 1 108 #define TCG_TARGET_HAS_shi_vec 0 109 #define TCG_TARGET_HAS_shs_vec 0 110 #define TCG_TARGET_HAS_shv_vec 1 111 #define TCG_TARGET_HAS_mul_vec 1 112 #define TCG_TARGET_HAS_sat_vec 1 113 #define TCG_TARGET_HAS_minmax_vec 1 114 #define TCG_TARGET_HAS_bitsel_vec have_vsx 115 #define TCG_TARGET_HAS_cmpsel_vec 1 116 #define TCG_TARGET_HAS_tst_vec 0 117 118 #define TCG_TARGET_extract_valid(type, ofs, len) 1 119 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 120 121 static inline bool 122 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 123 { 124 if (type == TCG_TYPE_I64 && ofs + len == 32) { 125 return true; 126 } 127 return ofs == 0 && (len == 8 || len == 16); 128 } 129 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 130 131 #endif 132