xref: /qemu/tcg/ppc/tcg-target-has.h (revision 18bc92091641880121d43584093ff207b0c44cfb)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Define target-specific opcode support
4  * Copyright (c) 2008 Fabrice Bellard
5  */
6 
7 #ifndef TCG_TARGET_HAS_H
8 #define TCG_TARGET_HAS_H
9 
10 #include "host/cpuinfo.h"
11 
12 #define have_isa_2_06  (cpuinfo & CPUINFO_V2_06)
13 #define have_isa_2_07  (cpuinfo & CPUINFO_V2_07)
14 #define have_isa_3_00  (cpuinfo & CPUINFO_V3_0)
15 #define have_isa_3_10  (cpuinfo & CPUINFO_V3_1)
16 #define have_altivec   (cpuinfo & CPUINFO_ALTIVEC)
17 #define have_vsx       (cpuinfo & CPUINFO_VSX)
18 
19 /* optional instructions */
20 #define TCG_TARGET_HAS_div_i32          1
21 #define TCG_TARGET_HAS_rem_i32          have_isa_3_00
22 #define TCG_TARGET_HAS_rot_i32          1
23 #define TCG_TARGET_HAS_bswap16_i32      1
24 #define TCG_TARGET_HAS_bswap32_i32      1
25 #define TCG_TARGET_HAS_not_i32          1
26 #define TCG_TARGET_HAS_nand_i32         1
27 #define TCG_TARGET_HAS_nor_i32          1
28 #define TCG_TARGET_HAS_clz_i32          1
29 #define TCG_TARGET_HAS_ctz_i32          have_isa_3_00
30 #define TCG_TARGET_HAS_ctpop_i32        have_isa_2_06
31 #define TCG_TARGET_HAS_extract2_i32     0
32 #define TCG_TARGET_HAS_negsetcond_i32   1
33 #define TCG_TARGET_HAS_mulu2_i32        0
34 #define TCG_TARGET_HAS_muls2_i32        0
35 #define TCG_TARGET_HAS_muluh_i32        1
36 #define TCG_TARGET_HAS_mulsh_i32        1
37 #define TCG_TARGET_HAS_qemu_st8_i32     0
38 
39 #if TCG_TARGET_REG_BITS == 64
40 #define TCG_TARGET_HAS_add2_i32         0
41 #define TCG_TARGET_HAS_sub2_i32         0
42 #define TCG_TARGET_HAS_extr_i64_i32     0
43 #define TCG_TARGET_HAS_div_i64          1
44 #define TCG_TARGET_HAS_rem_i64          have_isa_3_00
45 #define TCG_TARGET_HAS_rot_i64          1
46 #define TCG_TARGET_HAS_bswap16_i64      1
47 #define TCG_TARGET_HAS_bswap32_i64      1
48 #define TCG_TARGET_HAS_bswap64_i64      1
49 #define TCG_TARGET_HAS_not_i64          1
50 #define TCG_TARGET_HAS_nand_i64         1
51 #define TCG_TARGET_HAS_nor_i64          1
52 #define TCG_TARGET_HAS_clz_i64          1
53 #define TCG_TARGET_HAS_ctz_i64          have_isa_3_00
54 #define TCG_TARGET_HAS_ctpop_i64        have_isa_2_06
55 #define TCG_TARGET_HAS_extract2_i64     0
56 #define TCG_TARGET_HAS_negsetcond_i64   1
57 #define TCG_TARGET_HAS_add2_i64         1
58 #define TCG_TARGET_HAS_sub2_i64         1
59 #define TCG_TARGET_HAS_mulu2_i64        0
60 #define TCG_TARGET_HAS_muls2_i64        0
61 #define TCG_TARGET_HAS_muluh_i64        1
62 #define TCG_TARGET_HAS_mulsh_i64        1
63 #endif
64 
65 #define TCG_TARGET_HAS_qemu_ldst_i128   \
66     (TCG_TARGET_REG_BITS == 64 && have_isa_2_07)
67 
68 #define TCG_TARGET_HAS_tst              1
69 
70 /*
71  * While technically Altivec could support V64, it has no 64-bit store
72  * instruction and substituting two 32-bit stores makes the generated
73  * code quite large.
74  */
75 #define TCG_TARGET_HAS_v64              have_vsx
76 #define TCG_TARGET_HAS_v128             have_altivec
77 #define TCG_TARGET_HAS_v256             0
78 
79 #define TCG_TARGET_HAS_andc_vec         1
80 #define TCG_TARGET_HAS_orc_vec          have_isa_2_07
81 #define TCG_TARGET_HAS_nand_vec         have_isa_2_07
82 #define TCG_TARGET_HAS_nor_vec          1
83 #define TCG_TARGET_HAS_eqv_vec          have_isa_2_07
84 #define TCG_TARGET_HAS_not_vec          1
85 #define TCG_TARGET_HAS_neg_vec          have_isa_3_00
86 #define TCG_TARGET_HAS_abs_vec          0
87 #define TCG_TARGET_HAS_roti_vec         0
88 #define TCG_TARGET_HAS_rots_vec         0
89 #define TCG_TARGET_HAS_rotv_vec         1
90 #define TCG_TARGET_HAS_shi_vec          0
91 #define TCG_TARGET_HAS_shs_vec          0
92 #define TCG_TARGET_HAS_shv_vec          1
93 #define TCG_TARGET_HAS_mul_vec          1
94 #define TCG_TARGET_HAS_sat_vec          1
95 #define TCG_TARGET_HAS_minmax_vec       1
96 #define TCG_TARGET_HAS_bitsel_vec       have_vsx
97 #define TCG_TARGET_HAS_cmpsel_vec       1
98 #define TCG_TARGET_HAS_tst_vec          0
99 
100 #define TCG_TARGET_extract_valid(type, ofs, len)   1
101 #define TCG_TARGET_deposit_valid(type, ofs, len)   1
102 
103 static inline bool
104 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
105 {
106     if (type == TCG_TYPE_I64 && ofs + len == 32) {
107         return true;
108     }
109     return ofs == 0 && (len == 8 || len == 16);
110 }
111 #define TCG_TARGET_sextract_valid  tcg_target_sextract_valid
112 
113 #endif
114