1 /* 2 * TriCore emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "exec/translation-block.h" 24 #include "qemu/error-report.h" 25 #include "tcg/debug-assert.h" 26 #include "accel/tcg/cpu-ops.h" 27 28 static inline void set_feature(CPUTriCoreState *env, int feature) 29 { 30 env->features |= 1ULL << feature; 31 } 32 33 static const gchar *tricore_gdb_arch_name(CPUState *cs) 34 { 35 return "tricore"; 36 } 37 38 static void tricore_cpu_set_pc(CPUState *cs, vaddr value) 39 { 40 cpu_env(cs)->PC = value & ~(target_ulong)1; 41 } 42 43 static vaddr tricore_cpu_get_pc(CPUState *cs) 44 { 45 return cpu_env(cs)->PC; 46 } 47 48 void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, 49 uint64_t *cs_base, uint32_t *flags) 50 { 51 uint32_t new_flags = 0; 52 *pc = env->PC; 53 *cs_base = 0; 54 55 new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV, 56 extract32(env->PSW, 10, 2)); 57 *flags = new_flags; 58 } 59 60 static void tricore_cpu_synchronize_from_tb(CPUState *cs, 61 const TranslationBlock *tb) 62 { 63 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 64 cpu_env(cs)->PC = tb->pc; 65 } 66 67 static void tricore_restore_state_to_opc(CPUState *cs, 68 const TranslationBlock *tb, 69 const uint64_t *data) 70 { 71 cpu_env(cs)->PC = data[0]; 72 } 73 74 static void tricore_cpu_reset_hold(Object *obj, ResetType type) 75 { 76 CPUState *cs = CPU(obj); 77 TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(obj); 78 79 if (tcc->parent_phases.hold) { 80 tcc->parent_phases.hold(obj, type); 81 } 82 83 cpu_state_reset(cpu_env(cs)); 84 } 85 86 static bool tricore_cpu_has_work(CPUState *cs) 87 { 88 return true; 89 } 90 91 static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch) 92 { 93 return 0; 94 } 95 96 static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) 97 { 98 CPUState *cs = CPU(dev); 99 TriCoreCPU *cpu = TRICORE_CPU(dev); 100 TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev); 101 CPUTriCoreState *env = &cpu->env; 102 Error *local_err = NULL; 103 104 cpu_exec_realizefn(cs, &local_err); 105 if (local_err != NULL) { 106 error_propagate(errp, local_err); 107 return; 108 } 109 110 /* Some features automatically imply others */ 111 if (tricore_has_feature(env, TRICORE_FEATURE_162)) { 112 set_feature(env, TRICORE_FEATURE_161); 113 } 114 115 if (tricore_has_feature(env, TRICORE_FEATURE_161)) { 116 set_feature(env, TRICORE_FEATURE_16); 117 } 118 119 if (tricore_has_feature(env, TRICORE_FEATURE_16)) { 120 set_feature(env, TRICORE_FEATURE_131); 121 } 122 if (tricore_has_feature(env, TRICORE_FEATURE_131)) { 123 set_feature(env, TRICORE_FEATURE_13); 124 } 125 cpu_reset(cs); 126 qemu_init_vcpu(cs); 127 128 tcc->parent_realize(dev, errp); 129 } 130 131 static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model) 132 { 133 ObjectClass *oc; 134 char *typename; 135 136 typename = g_strdup_printf(TRICORE_CPU_TYPE_NAME("%s"), cpu_model); 137 oc = object_class_by_name(typename); 138 g_free(typename); 139 140 return oc; 141 } 142 143 static void tc1796_initfn(Object *obj) 144 { 145 TriCoreCPU *cpu = TRICORE_CPU(obj); 146 147 set_feature(&cpu->env, TRICORE_FEATURE_13); 148 } 149 150 static void tc1797_initfn(Object *obj) 151 { 152 TriCoreCPU *cpu = TRICORE_CPU(obj); 153 154 set_feature(&cpu->env, TRICORE_FEATURE_131); 155 } 156 157 static void tc27x_initfn(Object *obj) 158 { 159 TriCoreCPU *cpu = TRICORE_CPU(obj); 160 161 set_feature(&cpu->env, TRICORE_FEATURE_161); 162 } 163 164 static void tc37x_initfn(Object *obj) 165 { 166 TriCoreCPU *cpu = TRICORE_CPU(obj); 167 168 set_feature(&cpu->env, TRICORE_FEATURE_162); 169 } 170 171 static bool tricore_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 172 { 173 /* Interrupts are not implemented */ 174 return false; 175 } 176 177 #include "hw/core/sysemu-cpu-ops.h" 178 179 static const struct SysemuCPUOps tricore_sysemu_ops = { 180 .has_work = tricore_cpu_has_work, 181 .get_phys_page_debug = tricore_cpu_get_phys_page_debug, 182 }; 183 184 static const TCGCPUOps tricore_tcg_ops = { 185 /* MTTCG not yet supported: require strict ordering */ 186 .guest_default_memory_order = TCG_MO_ALL, 187 .mttcg_supported = false, 188 .initialize = tricore_tcg_init, 189 .translate_code = tricore_translate_code, 190 .synchronize_from_tb = tricore_cpu_synchronize_from_tb, 191 .restore_state_to_opc = tricore_restore_state_to_opc, 192 .mmu_index = tricore_cpu_mmu_index, 193 .tlb_fill = tricore_cpu_tlb_fill, 194 .cpu_exec_interrupt = tricore_cpu_exec_interrupt, 195 .cpu_exec_halt = tricore_cpu_has_work, 196 .cpu_exec_reset = cpu_reset, 197 }; 198 199 static void tricore_cpu_class_init(ObjectClass *c, const void *data) 200 { 201 TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c); 202 CPUClass *cc = CPU_CLASS(c); 203 DeviceClass *dc = DEVICE_CLASS(c); 204 ResettableClass *rc = RESETTABLE_CLASS(c); 205 206 device_class_set_parent_realize(dc, tricore_cpu_realizefn, 207 &mcc->parent_realize); 208 209 resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL, 210 &mcc->parent_phases); 211 cc->class_by_name = tricore_cpu_class_by_name; 212 213 cc->gdb_read_register = tricore_cpu_gdb_read_register; 214 cc->gdb_write_register = tricore_cpu_gdb_write_register; 215 cc->gdb_num_core_regs = 44; 216 cc->gdb_arch_name = tricore_gdb_arch_name; 217 218 cc->dump_state = tricore_cpu_dump_state; 219 cc->set_pc = tricore_cpu_set_pc; 220 cc->get_pc = tricore_cpu_get_pc; 221 cc->sysemu_ops = &tricore_sysemu_ops; 222 cc->tcg_ops = &tricore_tcg_ops; 223 } 224 225 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ 226 { \ 227 .parent = TYPE_TRICORE_CPU, \ 228 .instance_init = initfn, \ 229 .name = TRICORE_CPU_TYPE_NAME(cpu_model), \ 230 } 231 232 static const TypeInfo tricore_cpu_type_infos[] = { 233 { 234 .name = TYPE_TRICORE_CPU, 235 .parent = TYPE_CPU, 236 .instance_size = sizeof(TriCoreCPU), 237 .instance_align = __alignof(TriCoreCPU), 238 .abstract = true, 239 .class_size = sizeof(TriCoreCPUClass), 240 .class_init = tricore_cpu_class_init, 241 }, 242 DEFINE_TRICORE_CPU_TYPE("tc1796", tc1796_initfn), 243 DEFINE_TRICORE_CPU_TYPE("tc1797", tc1797_initfn), 244 DEFINE_TRICORE_CPU_TYPE("tc27x", tc27x_initfn), 245 DEFINE_TRICORE_CPU_TYPE("tc37x", tc37x_initfn), 246 }; 247 248 DEFINE_TYPES(tricore_cpu_type_infos) 249