1 /* 2 * TriCore emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "exec/translation-block.h" 25 #include "qemu/error-report.h" 26 #include "tcg/debug-assert.h" 27 28 static inline void set_feature(CPUTriCoreState *env, int feature) 29 { 30 env->features |= 1ULL << feature; 31 } 32 33 static const gchar *tricore_gdb_arch_name(CPUState *cs) 34 { 35 return "tricore"; 36 } 37 38 static void tricore_cpu_set_pc(CPUState *cs, vaddr value) 39 { 40 cpu_env(cs)->PC = value & ~(target_ulong)1; 41 } 42 43 static vaddr tricore_cpu_get_pc(CPUState *cs) 44 { 45 return cpu_env(cs)->PC; 46 } 47 48 static void tricore_cpu_synchronize_from_tb(CPUState *cs, 49 const TranslationBlock *tb) 50 { 51 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 52 cpu_env(cs)->PC = tb->pc; 53 } 54 55 static void tricore_restore_state_to_opc(CPUState *cs, 56 const TranslationBlock *tb, 57 const uint64_t *data) 58 { 59 cpu_env(cs)->PC = data[0]; 60 } 61 62 static void tricore_cpu_reset_hold(Object *obj, ResetType type) 63 { 64 CPUState *cs = CPU(obj); 65 TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(obj); 66 67 if (tcc->parent_phases.hold) { 68 tcc->parent_phases.hold(obj, type); 69 } 70 71 cpu_state_reset(cpu_env(cs)); 72 } 73 74 static bool tricore_cpu_has_work(CPUState *cs) 75 { 76 return true; 77 } 78 79 static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch) 80 { 81 return 0; 82 } 83 84 static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) 85 { 86 CPUState *cs = CPU(dev); 87 TriCoreCPU *cpu = TRICORE_CPU(dev); 88 TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev); 89 CPUTriCoreState *env = &cpu->env; 90 Error *local_err = NULL; 91 92 cpu_exec_realizefn(cs, &local_err); 93 if (local_err != NULL) { 94 error_propagate(errp, local_err); 95 return; 96 } 97 98 /* Some features automatically imply others */ 99 if (tricore_has_feature(env, TRICORE_FEATURE_162)) { 100 set_feature(env, TRICORE_FEATURE_161); 101 } 102 103 if (tricore_has_feature(env, TRICORE_FEATURE_161)) { 104 set_feature(env, TRICORE_FEATURE_16); 105 } 106 107 if (tricore_has_feature(env, TRICORE_FEATURE_16)) { 108 set_feature(env, TRICORE_FEATURE_131); 109 } 110 if (tricore_has_feature(env, TRICORE_FEATURE_131)) { 111 set_feature(env, TRICORE_FEATURE_13); 112 } 113 cpu_reset(cs); 114 qemu_init_vcpu(cs); 115 116 tcc->parent_realize(dev, errp); 117 } 118 119 static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model) 120 { 121 ObjectClass *oc; 122 char *typename; 123 124 typename = g_strdup_printf(TRICORE_CPU_TYPE_NAME("%s"), cpu_model); 125 oc = object_class_by_name(typename); 126 g_free(typename); 127 128 return oc; 129 } 130 131 static void tc1796_initfn(Object *obj) 132 { 133 TriCoreCPU *cpu = TRICORE_CPU(obj); 134 135 set_feature(&cpu->env, TRICORE_FEATURE_13); 136 } 137 138 static void tc1797_initfn(Object *obj) 139 { 140 TriCoreCPU *cpu = TRICORE_CPU(obj); 141 142 set_feature(&cpu->env, TRICORE_FEATURE_131); 143 } 144 145 static void tc27x_initfn(Object *obj) 146 { 147 TriCoreCPU *cpu = TRICORE_CPU(obj); 148 149 set_feature(&cpu->env, TRICORE_FEATURE_161); 150 } 151 152 static void tc37x_initfn(Object *obj) 153 { 154 TriCoreCPU *cpu = TRICORE_CPU(obj); 155 156 set_feature(&cpu->env, TRICORE_FEATURE_162); 157 } 158 159 static bool tricore_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 160 { 161 /* Interrupts are not implemented */ 162 return false; 163 } 164 165 #include "hw/core/sysemu-cpu-ops.h" 166 167 static const struct SysemuCPUOps tricore_sysemu_ops = { 168 .get_phys_page_debug = tricore_cpu_get_phys_page_debug, 169 }; 170 171 #include "hw/core/tcg-cpu-ops.h" 172 173 static const TCGCPUOps tricore_tcg_ops = { 174 .initialize = tricore_tcg_init, 175 .translate_code = tricore_translate_code, 176 .synchronize_from_tb = tricore_cpu_synchronize_from_tb, 177 .restore_state_to_opc = tricore_restore_state_to_opc, 178 .tlb_fill = tricore_cpu_tlb_fill, 179 .cpu_exec_interrupt = tricore_cpu_exec_interrupt, 180 .cpu_exec_halt = tricore_cpu_has_work, 181 }; 182 183 static void tricore_cpu_class_init(ObjectClass *c, void *data) 184 { 185 TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c); 186 CPUClass *cc = CPU_CLASS(c); 187 DeviceClass *dc = DEVICE_CLASS(c); 188 ResettableClass *rc = RESETTABLE_CLASS(c); 189 190 device_class_set_parent_realize(dc, tricore_cpu_realizefn, 191 &mcc->parent_realize); 192 193 resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL, 194 &mcc->parent_phases); 195 cc->class_by_name = tricore_cpu_class_by_name; 196 cc->has_work = tricore_cpu_has_work; 197 cc->mmu_index = tricore_cpu_mmu_index; 198 199 cc->gdb_read_register = tricore_cpu_gdb_read_register; 200 cc->gdb_write_register = tricore_cpu_gdb_write_register; 201 cc->gdb_num_core_regs = 44; 202 cc->gdb_arch_name = tricore_gdb_arch_name; 203 204 cc->dump_state = tricore_cpu_dump_state; 205 cc->set_pc = tricore_cpu_set_pc; 206 cc->get_pc = tricore_cpu_get_pc; 207 cc->sysemu_ops = &tricore_sysemu_ops; 208 cc->tcg_ops = &tricore_tcg_ops; 209 } 210 211 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ 212 { \ 213 .parent = TYPE_TRICORE_CPU, \ 214 .instance_init = initfn, \ 215 .name = TRICORE_CPU_TYPE_NAME(cpu_model), \ 216 } 217 218 static const TypeInfo tricore_cpu_type_infos[] = { 219 { 220 .name = TYPE_TRICORE_CPU, 221 .parent = TYPE_CPU, 222 .instance_size = sizeof(TriCoreCPU), 223 .instance_align = __alignof(TriCoreCPU), 224 .abstract = true, 225 .class_size = sizeof(TriCoreCPUClass), 226 .class_init = tricore_cpu_class_init, 227 }, 228 DEFINE_TRICORE_CPU_TYPE("tc1796", tc1796_initfn), 229 DEFINE_TRICORE_CPU_TYPE("tc1797", tc1797_initfn), 230 DEFINE_TRICORE_CPU_TYPE("tc27x", tc27x_initfn), 231 DEFINE_TRICORE_CPU_TYPE("tc37x", tc37x_initfn), 232 }; 233 234 DEFINE_TYPES(tricore_cpu_type_infos) 235