1 /* 2 * PowerPC implementation of KVM hooks 3 * 4 * Copyright IBM Corp. 2007 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * Authors: 8 * Jerone Young <jyoung5@us.ibm.com> 9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 10 * Hollis Blanchard <hollisb@us.ibm.com> 11 * 12 * This work is licensed under the terms of the GNU GPL, version 2 or later. 13 * See the COPYING file in the top-level directory. 14 * 15 */ 16 17 #include "qemu/osdep.h" 18 #include <dirent.h> 19 #include <sys/ioctl.h> 20 #include <sys/vfs.h> 21 22 #include <linux/kvm.h> 23 24 #include "qapi/error.h" 25 #include "qemu/error-report.h" 26 #include "cpu.h" 27 #include "cpu-models.h" 28 #include "qemu/timer.h" 29 #include "system/hw_accel.h" 30 #include "kvm_ppc.h" 31 #include "system/cpus.h" 32 #include "system/device_tree.h" 33 #include "mmu-hash64.h" 34 35 #include "hw/ppc/spapr.h" 36 #include "hw/ppc/spapr_cpu_core.h" 37 #include "hw/hw.h" 38 #include "hw/ppc/ppc.h" 39 #include "migration/qemu-file-types.h" 40 #include "system/watchdog.h" 41 #include "trace.h" 42 #include "gdbstub/enums.h" 43 #include "exec/memattrs.h" 44 #include "system/ram_addr.h" 45 #include "system/hostmem.h" 46 #include "qemu/cutils.h" 47 #include "qemu/main-loop.h" 48 #include "qemu/mmap-alloc.h" 49 #include "elf.h" 50 #include "system/kvm_int.h" 51 #include "system/kvm.h" 52 #include "accel/accel-cpu-target.h" 53 54 #include CONFIG_DEVICES 55 56 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" 57 58 #define DEBUG_RETURN_GUEST 0 59 #define DEBUG_RETURN_GDB 1 60 61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 62 KVM_CAP_LAST_INFO 63 }; 64 65 static int cap_interrupt_unset; 66 static int cap_segstate; 67 static int cap_booke_sregs; 68 static int cap_ppc_smt; 69 static int cap_ppc_smt_possible; 70 static int cap_spapr_tce; 71 static int cap_spapr_tce_64; 72 static int cap_spapr_multitce; 73 static int cap_spapr_vfio; 74 static int cap_hior; 75 static int cap_one_reg; 76 static int cap_epr; 77 static int cap_ppc_watchdog; 78 static int cap_htab_fd; 79 static int cap_fixup_hcalls; 80 static int cap_htm; /* Hardware transactional memory support */ 81 static int cap_mmu_radix; 82 static int cap_mmu_hash_v3; 83 static int cap_xive; 84 static int cap_resize_hpt; 85 static int cap_ppc_pvr_compat; 86 static int cap_ppc_safe_cache; 87 static int cap_ppc_safe_bounds_check; 88 static int cap_ppc_safe_indirect_branch; 89 static int cap_ppc_count_cache_flush_assist; 90 static int cap_ppc_nested_kvm_hv; 91 static int cap_large_decr; 92 static int cap_fwnmi; 93 static int cap_rpt_invalidate; 94 static int cap_ail_mode_3; 95 static int cap_dawr1; 96 97 #ifdef CONFIG_PSERIES 98 static int cap_papr; 99 #else 100 #define cap_papr (0) 101 #endif 102 103 static uint32_t debug_inst_opcode; 104 105 /* 106 * Check whether we are running with KVM-PR (instead of KVM-HV). This 107 * should only be used for fallback tests - generally we should use 108 * explicit capabilities for the features we want, rather than 109 * assuming what is/isn't available depending on the KVM variant. 110 */ 111 static bool kvmppc_is_pr(KVMState *ks) 112 { 113 /* Assume KVM-PR if the GET_PVINFO capability is available */ 114 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0; 115 } 116 117 static int kvm_ppc_register_host_cpu_type(void); 118 static void kvmppc_get_cpu_characteristics(KVMState *s); 119 static int kvmppc_get_dec_bits(void); 120 121 int kvm_arch_get_default_type(MachineState *ms) 122 { 123 return 0; 124 } 125 126 int kvm_arch_init(MachineState *ms, KVMState *s) 127 { 128 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); 129 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); 130 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); 131 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE); 132 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); 133 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64); 134 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE); 135 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO); 136 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); 137 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); 138 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); 139 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); 140 /* 141 * Note: we don't set cap_papr here, because this capability is 142 * only activated after this by kvmppc_set_papr() 143 */ 144 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD); 145 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL); 146 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT); 147 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM); 148 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX); 149 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3); 150 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE); 151 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT); 152 kvmppc_get_cpu_characteristics(s); 153 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV); 154 cap_large_decr = kvmppc_get_dec_bits(); 155 cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI); 156 cap_dawr1 = kvm_vm_check_extension(s, KVM_CAP_PPC_DAWR1); 157 /* 158 * Note: setting it to false because there is not such capability 159 * in KVM at this moment. 160 * 161 * TODO: call kvm_vm_check_extension() with the right capability 162 * after the kernel starts implementing it. 163 */ 164 cap_ppc_pvr_compat = false; 165 166 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) { 167 error_report("KVM: Host kernel doesn't have level irq capability"); 168 exit(1); 169 } 170 171 cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE); 172 cap_ail_mode_3 = kvm_vm_check_extension(s, KVM_CAP_PPC_AIL_MODE_3); 173 kvm_ppc_register_host_cpu_type(); 174 175 return 0; 176 } 177 178 int kvm_arch_irqchip_create(KVMState *s) 179 { 180 return 0; 181 } 182 183 static int kvm_arch_sync_sregs(PowerPCCPU *cpu) 184 { 185 CPUPPCState *cenv = &cpu->env; 186 CPUState *cs = CPU(cpu); 187 struct kvm_sregs sregs; 188 int ret; 189 190 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 191 /* 192 * What we're really trying to say is "if we're on BookE, we 193 * use the native PVR for now". This is the only sane way to 194 * check it though, so we potentially confuse users that they 195 * can run BookE guests on BookS. Let's hope nobody dares 196 * enough :) 197 */ 198 return 0; 199 } else { 200 if (!cap_segstate) { 201 fprintf(stderr, "kvm error: missing PVR setting capability\n"); 202 return -ENOSYS; 203 } 204 } 205 206 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); 207 if (ret) { 208 return ret; 209 } 210 211 sregs.pvr = cenv->spr[SPR_PVR]; 212 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); 213 } 214 215 /* Set up a shared TLB array with KVM */ 216 static int kvm_booke206_tlb_init(PowerPCCPU *cpu) 217 { 218 CPUPPCState *env = &cpu->env; 219 CPUState *cs = CPU(cpu); 220 struct kvm_book3e_206_tlb_params params = {}; 221 struct kvm_config_tlb cfg = {}; 222 unsigned int entries = 0; 223 int ret, i; 224 225 if (!kvm_enabled() || 226 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { 227 return 0; 228 } 229 230 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); 231 232 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 233 params.tlb_sizes[i] = booke206_tlb_size(env, i); 234 params.tlb_ways[i] = booke206_tlb_ways(env, i); 235 entries += params.tlb_sizes[i]; 236 } 237 238 assert(entries == env->nb_tlb); 239 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); 240 241 env->tlb_dirty = true; 242 243 cfg.array = (uintptr_t)env->tlb.tlbm; 244 cfg.array_len = sizeof(ppcmas_tlb_t) * entries; 245 cfg.params = (uintptr_t)¶ms; 246 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; 247 248 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg); 249 if (ret < 0) { 250 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", 251 __func__, strerror(-ret)); 252 return ret; 253 } 254 255 env->kvm_sw_tlb = true; 256 return 0; 257 } 258 259 260 #if defined(TARGET_PPC64) 261 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp) 262 { 263 int ret; 264 265 assert(kvm_state != NULL); 266 267 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) { 268 error_setg(errp, "KVM doesn't expose the MMU features it supports"); 269 error_append_hint(errp, "Consider switching to a newer KVM\n"); 270 return; 271 } 272 273 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info); 274 if (ret == 0) { 275 return; 276 } 277 278 error_setg_errno(errp, -ret, 279 "KVM failed to provide the MMU features it supports"); 280 } 281 282 static struct ppc_radix_page_info *kvmppc_get_radix_page_info(void) 283 { 284 KVMState *s = KVM_STATE(current_accel()); 285 struct ppc_radix_page_info *radix_page_info; 286 struct kvm_ppc_rmmu_info rmmu_info = { }; 287 int i; 288 289 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) { 290 return NULL; 291 } 292 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) { 293 return NULL; 294 } 295 radix_page_info = g_malloc0(sizeof(*radix_page_info)); 296 radix_page_info->count = 0; 297 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 298 if (rmmu_info.ap_encodings[i]) { 299 radix_page_info->entries[i] = rmmu_info.ap_encodings[i]; 300 radix_page_info->count++; 301 } 302 } 303 return radix_page_info; 304 } 305 306 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu, 307 bool radix, bool gtse, 308 uint64_t proc_tbl) 309 { 310 CPUState *cs = CPU(cpu); 311 int ret; 312 uint64_t flags = 0; 313 struct kvm_ppc_mmuv3_cfg cfg = { 314 .process_table = proc_tbl, 315 }; 316 317 if (radix) { 318 flags |= KVM_PPC_MMUV3_RADIX; 319 } 320 if (gtse) { 321 flags |= KVM_PPC_MMUV3_GTSE; 322 } 323 cfg.flags = flags; 324 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg); 325 switch (ret) { 326 case 0: 327 return H_SUCCESS; 328 case -EINVAL: 329 return H_PARAMETER; 330 case -ENODEV: 331 return H_NOT_AVAILABLE; 332 default: 333 return H_HARDWARE; 334 } 335 } 336 337 bool kvmppc_hpt_needs_host_contiguous_pages(void) 338 { 339 static struct kvm_ppc_smmu_info smmu_info; 340 341 if (!kvm_enabled()) { 342 return false; 343 } 344 345 kvm_get_smmu_info(&smmu_info, &error_fatal); 346 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL); 347 } 348 349 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp) 350 { 351 struct kvm_ppc_smmu_info smmu_info; 352 int iq, ik, jq, jk; 353 Error *local_err = NULL; 354 355 /* For now, we only have anything to check on hash64 MMUs */ 356 if (!cpu->hash64_opts || !kvm_enabled()) { 357 return; 358 } 359 360 kvm_get_smmu_info(&smmu_info, &local_err); 361 if (local_err) { 362 error_propagate(errp, local_err); 363 return; 364 } 365 366 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG) 367 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { 368 error_setg(errp, 369 "KVM does not support 1TiB segments which guest expects"); 370 return; 371 } 372 373 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) { 374 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u", 375 smmu_info.slb_size, cpu->hash64_opts->slb_size); 376 return; 377 } 378 379 /* 380 * Verify that every pagesize supported by the cpu model is 381 * supported by KVM with the same encodings 382 */ 383 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) { 384 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq]; 385 struct kvm_ppc_one_seg_page_size *ksps; 386 387 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) { 388 if (qsps->page_shift == smmu_info.sps[ik].page_shift) { 389 break; 390 } 391 } 392 if (ik >= ARRAY_SIZE(smmu_info.sps)) { 393 error_setg(errp, "KVM doesn't support for base page shift %u", 394 qsps->page_shift); 395 return; 396 } 397 398 ksps = &smmu_info.sps[ik]; 399 if (ksps->slb_enc != qsps->slb_enc) { 400 error_setg(errp, 401 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x", 402 ksps->slb_enc, ksps->page_shift, qsps->slb_enc); 403 return; 404 } 405 406 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) { 407 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) { 408 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) { 409 break; 410 } 411 } 412 413 if (jk >= ARRAY_SIZE(ksps->enc)) { 414 error_setg(errp, "KVM doesn't support page shift %u/%u", 415 qsps->enc[jq].page_shift, qsps->page_shift); 416 return; 417 } 418 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) { 419 error_setg(errp, 420 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x", 421 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift, 422 qsps->page_shift, qsps->enc[jq].pte_enc); 423 return; 424 } 425 } 426 } 427 428 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 429 /* 430 * Mostly what guest pagesizes we can use are related to the 431 * host pages used to map guest RAM, which is handled in the 432 * platform code. Cache-Inhibited largepages (64k) however are 433 * used for I/O, so if they're mapped to the host at all it 434 * will be a normal mapping, not a special hugepage one used 435 * for RAM. 436 */ 437 if (qemu_real_host_page_size() < 0x10000) { 438 error_setg(errp, 439 "KVM can't supply 64kiB CI pages, which guest expects"); 440 } 441 } 442 } 443 #endif /* !defined (TARGET_PPC64) */ 444 445 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 446 { 447 return POWERPC_CPU(cpu)->vcpu_id; 448 } 449 450 /* 451 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports 452 * only 1 watchpoint, so array size of 4 is sufficient for now. 453 */ 454 #define MAX_HW_BKPTS 4 455 456 static struct HWBreakpoint { 457 target_ulong addr; 458 int type; 459 } hw_debug_points[MAX_HW_BKPTS]; 460 461 static CPUWatchpoint hw_watchpoint; 462 463 /* Default there is no breakpoint and watchpoint supported */ 464 static int max_hw_breakpoint; 465 static int max_hw_watchpoint; 466 static int nb_hw_breakpoint; 467 static int nb_hw_watchpoint; 468 469 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv) 470 { 471 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 472 max_hw_breakpoint = 2; 473 max_hw_watchpoint = 2; 474 } 475 476 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) { 477 fprintf(stderr, "Error initializing h/w breakpoints\n"); 478 return; 479 } 480 } 481 482 int kvm_arch_init_vcpu(CPUState *cs) 483 { 484 PowerPCCPU *cpu = POWERPC_CPU(cs); 485 CPUPPCState *cenv = &cpu->env; 486 int ret; 487 488 /* Synchronize sregs with kvm */ 489 ret = kvm_arch_sync_sregs(cpu); 490 if (ret) { 491 if (ret == -EINVAL) { 492 error_report("Register sync failed... If you're using kvm-hv.ko," 493 " only \"-cpu host\" is possible"); 494 } 495 return ret; 496 } 497 498 switch (cenv->mmu_model) { 499 case POWERPC_MMU_BOOKE206: 500 /* This target supports access to KVM's guest TLB */ 501 ret = kvm_booke206_tlb_init(cpu); 502 break; 503 case POWERPC_MMU_2_07: 504 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) { 505 /* 506 * KVM-HV has transactional memory on POWER8 also without 507 * the KVM_CAP_PPC_HTM extension, so enable it here 508 * instead as long as it's available to userspace on the 509 * host. 510 */ 511 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) { 512 cap_htm = true; 513 } 514 } 515 break; 516 default: 517 break; 518 } 519 520 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode); 521 kvmppc_hw_debug_points_init(cenv); 522 523 return ret; 524 } 525 526 int kvm_arch_destroy_vcpu(CPUState *cs) 527 { 528 return 0; 529 } 530 531 static void kvm_sw_tlb_put(PowerPCCPU *cpu) 532 { 533 CPUPPCState *env = &cpu->env; 534 CPUState *cs = CPU(cpu); 535 struct kvm_dirty_tlb dirty_tlb; 536 unsigned char *bitmap; 537 int ret; 538 539 if (!env->kvm_sw_tlb) { 540 return; 541 } 542 543 bitmap = g_malloc((env->nb_tlb + 7) / 8); 544 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); 545 546 dirty_tlb.bitmap = (uintptr_t)bitmap; 547 dirty_tlb.num_dirty = env->nb_tlb; 548 549 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); 550 if (ret) { 551 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", 552 __func__, strerror(-ret)); 553 } 554 555 g_free(bitmap); 556 } 557 558 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) 559 { 560 CPUPPCState *env = cpu_env(cs); 561 /* Init 'val' to avoid "uninitialised value" Valgrind warnings */ 562 union { 563 uint32_t u32; 564 uint64_t u64; 565 } val = { }; 566 struct kvm_one_reg reg = { 567 .id = id, 568 .addr = (uintptr_t) &val, 569 }; 570 int ret; 571 572 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 573 if (ret != 0) { 574 trace_kvm_failed_spr_get(spr, strerror(errno)); 575 } else { 576 switch (id & KVM_REG_SIZE_MASK) { 577 case KVM_REG_SIZE_U32: 578 env->spr[spr] = val.u32; 579 break; 580 581 case KVM_REG_SIZE_U64: 582 env->spr[spr] = val.u64; 583 break; 584 585 default: 586 /* Don't handle this size yet */ 587 abort(); 588 } 589 } 590 } 591 592 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) 593 { 594 CPUPPCState *env = cpu_env(cs); 595 union { 596 uint32_t u32; 597 uint64_t u64; 598 } val; 599 struct kvm_one_reg reg = { 600 .id = id, 601 .addr = (uintptr_t) &val, 602 }; 603 int ret; 604 605 switch (id & KVM_REG_SIZE_MASK) { 606 case KVM_REG_SIZE_U32: 607 val.u32 = env->spr[spr]; 608 break; 609 610 case KVM_REG_SIZE_U64: 611 val.u64 = env->spr[spr]; 612 break; 613 614 default: 615 /* Don't handle this size yet */ 616 abort(); 617 } 618 619 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 620 if (ret != 0) { 621 trace_kvm_failed_spr_set(spr, strerror(errno)); 622 } 623 } 624 625 static int kvm_put_fp(CPUState *cs) 626 { 627 CPUPPCState *env = cpu_env(cs); 628 struct kvm_one_reg reg; 629 int i; 630 int ret; 631 632 if (env->insns_flags & PPC_FLOAT) { 633 uint64_t fpscr = env->fpscr; 634 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 635 636 reg.id = KVM_REG_PPC_FPSCR; 637 reg.addr = (uintptr_t)&fpscr; 638 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 639 if (ret < 0) { 640 trace_kvm_failed_fpscr_set(strerror(errno)); 641 return ret; 642 } 643 644 for (i = 0; i < 32; i++) { 645 uint64_t vsr[2]; 646 uint64_t *fpr = cpu_fpr_ptr(env, i); 647 uint64_t *vsrl = cpu_vsrl_ptr(env, i); 648 649 #if HOST_BIG_ENDIAN 650 vsr[0] = float64_val(*fpr); 651 vsr[1] = *vsrl; 652 #else 653 vsr[0] = *vsrl; 654 vsr[1] = float64_val(*fpr); 655 #endif 656 reg.addr = (uintptr_t) &vsr; 657 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 658 659 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 660 if (ret < 0) { 661 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i, 662 strerror(errno)); 663 return ret; 664 } 665 } 666 } 667 668 if (env->insns_flags & PPC_ALTIVEC) { 669 reg.id = KVM_REG_PPC_VSCR; 670 reg.addr = (uintptr_t)&env->vscr; 671 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 672 if (ret < 0) { 673 trace_kvm_failed_vscr_set(strerror(errno)); 674 return ret; 675 } 676 677 for (i = 0; i < 32; i++) { 678 reg.id = KVM_REG_PPC_VR(i); 679 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 680 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 681 if (ret < 0) { 682 trace_kvm_failed_vr_set(i, strerror(errno)); 683 return ret; 684 } 685 } 686 } 687 688 return 0; 689 } 690 691 static int kvm_get_fp(CPUState *cs) 692 { 693 CPUPPCState *env = cpu_env(cs); 694 struct kvm_one_reg reg; 695 int i; 696 int ret; 697 698 if (env->insns_flags & PPC_FLOAT) { 699 uint64_t fpscr; 700 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 701 702 reg.id = KVM_REG_PPC_FPSCR; 703 reg.addr = (uintptr_t)&fpscr; 704 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 705 if (ret < 0) { 706 trace_kvm_failed_fpscr_get(strerror(errno)); 707 return ret; 708 } else { 709 env->fpscr = fpscr; 710 } 711 712 for (i = 0; i < 32; i++) { 713 uint64_t vsr[2]; 714 uint64_t *fpr = cpu_fpr_ptr(env, i); 715 uint64_t *vsrl = cpu_vsrl_ptr(env, i); 716 717 reg.addr = (uintptr_t) &vsr; 718 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 719 720 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 721 if (ret < 0) { 722 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i, 723 strerror(errno)); 724 return ret; 725 } else { 726 #if HOST_BIG_ENDIAN 727 *fpr = vsr[0]; 728 if (vsx) { 729 *vsrl = vsr[1]; 730 } 731 #else 732 *fpr = vsr[1]; 733 if (vsx) { 734 *vsrl = vsr[0]; 735 } 736 #endif 737 } 738 } 739 } 740 741 if (env->insns_flags & PPC_ALTIVEC) { 742 reg.id = KVM_REG_PPC_VSCR; 743 reg.addr = (uintptr_t)&env->vscr; 744 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 745 if (ret < 0) { 746 trace_kvm_failed_vscr_get(strerror(errno)); 747 return ret; 748 } 749 750 for (i = 0; i < 32; i++) { 751 reg.id = KVM_REG_PPC_VR(i); 752 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 753 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 754 if (ret < 0) { 755 trace_kvm_failed_vr_get(i, strerror(errno)); 756 return ret; 757 } 758 } 759 } 760 761 return 0; 762 } 763 764 #if defined(TARGET_PPC64) 765 static int kvm_get_vpa(CPUState *cs) 766 { 767 PowerPCCPU *cpu = POWERPC_CPU(cs); 768 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 769 struct kvm_one_reg reg; 770 int ret; 771 772 reg.id = KVM_REG_PPC_VPA_ADDR; 773 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 774 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 775 if (ret < 0) { 776 trace_kvm_failed_vpa_addr_get(strerror(errno)); 777 return ret; 778 } 779 780 assert((uintptr_t)&spapr_cpu->slb_shadow_size 781 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 782 reg.id = KVM_REG_PPC_VPA_SLB; 783 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 784 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 785 if (ret < 0) { 786 trace_kvm_failed_slb_get(strerror(errno)); 787 return ret; 788 } 789 790 assert((uintptr_t)&spapr_cpu->dtl_size 791 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 792 reg.id = KVM_REG_PPC_VPA_DTL; 793 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 794 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 795 if (ret < 0) { 796 trace_kvm_failed_dtl_get(strerror(errno)); 797 return ret; 798 } 799 800 return 0; 801 } 802 803 static int kvm_put_vpa(CPUState *cs) 804 { 805 PowerPCCPU *cpu = POWERPC_CPU(cs); 806 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 807 struct kvm_one_reg reg; 808 int ret; 809 810 /* 811 * SLB shadow or DTL can't be registered unless a master VPA is 812 * registered. That means when restoring state, if a VPA *is* 813 * registered, we need to set that up first. If not, we need to 814 * deregister the others before deregistering the master VPA 815 */ 816 assert(spapr_cpu->vpa_addr 817 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr)); 818 819 if (spapr_cpu->vpa_addr) { 820 reg.id = KVM_REG_PPC_VPA_ADDR; 821 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 822 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 823 if (ret < 0) { 824 trace_kvm_failed_vpa_addr_set(strerror(errno)); 825 return ret; 826 } 827 } 828 829 assert((uintptr_t)&spapr_cpu->slb_shadow_size 830 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 831 reg.id = KVM_REG_PPC_VPA_SLB; 832 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 833 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 834 if (ret < 0) { 835 trace_kvm_failed_slb_set(strerror(errno)); 836 return ret; 837 } 838 839 assert((uintptr_t)&spapr_cpu->dtl_size 840 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 841 reg.id = KVM_REG_PPC_VPA_DTL; 842 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 843 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 844 if (ret < 0) { 845 trace_kvm_failed_dtl_set(strerror(errno)); 846 return ret; 847 } 848 849 if (!spapr_cpu->vpa_addr) { 850 reg.id = KVM_REG_PPC_VPA_ADDR; 851 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 852 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 853 if (ret < 0) { 854 trace_kvm_failed_null_vpa_addr_set(strerror(errno)); 855 return ret; 856 } 857 } 858 859 return 0; 860 } 861 #endif /* TARGET_PPC64 */ 862 863 int kvmppc_put_books_sregs(PowerPCCPU *cpu) 864 { 865 CPUPPCState *env = &cpu->env; 866 struct kvm_sregs sregs = { }; 867 int i; 868 869 sregs.pvr = env->spr[SPR_PVR]; 870 871 if (cpu->vhyp) { 872 sregs.u.s.sdr1 = cpu->vhyp_class->encode_hpt_for_kvm_pr(cpu->vhyp); 873 } else { 874 sregs.u.s.sdr1 = env->spr[SPR_SDR1]; 875 } 876 877 /* Sync SLB */ 878 #ifdef TARGET_PPC64 879 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 880 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; 881 if (env->slb[i].esid & SLB_ESID_V) { 882 sregs.u.s.ppc64.slb[i].slbe |= i; 883 } 884 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; 885 } 886 #endif 887 888 /* Sync SRs */ 889 for (i = 0; i < 16; i++) { 890 sregs.u.s.ppc32.sr[i] = env->sr[i]; 891 } 892 893 /* Sync BATs */ 894 for (i = 0; i < 8; i++) { 895 /* Beware. We have to swap upper and lower bits here */ 896 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) 897 | env->DBAT[1][i]; 898 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) 899 | env->IBAT[1][i]; 900 } 901 902 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); 903 } 904 905 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 906 { 907 PowerPCCPU *cpu = POWERPC_CPU(cs); 908 CPUPPCState *env = &cpu->env; 909 struct kvm_regs regs; 910 int ret; 911 int i; 912 913 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 914 if (ret < 0) { 915 return ret; 916 } 917 918 regs.ctr = env->ctr; 919 regs.lr = env->lr; 920 regs.xer = cpu_read_xer(env); 921 regs.msr = env->msr; 922 regs.pc = env->nip; 923 924 regs.srr0 = env->spr[SPR_SRR0]; 925 regs.srr1 = env->spr[SPR_SRR1]; 926 927 regs.sprg0 = env->spr[SPR_SPRG0]; 928 regs.sprg1 = env->spr[SPR_SPRG1]; 929 regs.sprg2 = env->spr[SPR_SPRG2]; 930 regs.sprg3 = env->spr[SPR_SPRG3]; 931 regs.sprg4 = env->spr[SPR_SPRG4]; 932 regs.sprg5 = env->spr[SPR_SPRG5]; 933 regs.sprg6 = env->spr[SPR_SPRG6]; 934 regs.sprg7 = env->spr[SPR_SPRG7]; 935 936 regs.pid = env->spr[SPR_BOOKE_PID]; 937 938 for (i = 0; i < 32; i++) { 939 regs.gpr[i] = env->gpr[i]; 940 } 941 942 regs.cr = ppc_get_cr(env); 943 944 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 945 if (ret < 0) { 946 return ret; 947 } 948 949 kvm_put_fp(cs); 950 951 if (env->tlb_dirty) { 952 kvm_sw_tlb_put(cpu); 953 env->tlb_dirty = false; 954 } 955 956 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) { 957 ret = kvmppc_put_books_sregs(cpu); 958 if (ret < 0) { 959 return ret; 960 } 961 } 962 963 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) { 964 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 965 } 966 967 if (cap_one_reg) { 968 /* 969 * We deliberately ignore errors here, for kernels which have 970 * the ONE_REG calls, but don't support the specific 971 * registers, there's a reasonable chance things will still 972 * work, at least until we try to migrate. 973 */ 974 for (i = 0; i < 1024; i++) { 975 uint64_t id = env->spr_cb[i].one_reg_id; 976 977 if (id != 0) { 978 kvm_put_one_spr(cs, id, i); 979 } 980 } 981 982 #ifdef TARGET_PPC64 983 if (FIELD_EX64(env->msr, MSR, TS)) { 984 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 986 } 987 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 989 } 990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 992 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 993 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 994 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 995 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 996 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 997 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 998 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 999 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 1000 } 1001 1002 if (cap_papr) { 1003 if (kvm_put_vpa(cs) < 0) { 1004 trace_kvm_failed_put_vpa(); 1005 } 1006 } 1007 1008 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1009 1010 if (level > KVM_PUT_RUNTIME_STATE) { 1011 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 1012 } 1013 #endif /* TARGET_PPC64 */ 1014 } 1015 1016 return ret; 1017 } 1018 1019 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor) 1020 { 1021 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR]; 1022 } 1023 1024 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu) 1025 { 1026 CPUPPCState *env = &cpu->env; 1027 struct kvm_sregs sregs; 1028 int ret; 1029 1030 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1031 if (ret < 0) { 1032 return ret; 1033 } 1034 1035 if (sregs.u.e.features & KVM_SREGS_E_BASE) { 1036 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; 1037 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; 1038 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; 1039 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; 1040 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; 1041 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; 1042 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; 1043 env->spr[SPR_DECR] = sregs.u.e.dec; 1044 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; 1045 env->spr[SPR_TBU] = sregs.u.e.tb >> 32; 1046 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; 1047 } 1048 1049 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { 1050 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; 1051 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; 1052 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; 1053 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; 1054 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; 1055 } 1056 1057 if (sregs.u.e.features & KVM_SREGS_E_64) { 1058 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; 1059 } 1060 1061 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { 1062 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; 1063 } 1064 1065 if (sregs.u.e.features & KVM_SREGS_E_IVOR) { 1066 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; 1067 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); 1068 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; 1069 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); 1070 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; 1071 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); 1072 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; 1073 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); 1074 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; 1075 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); 1076 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; 1077 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); 1078 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; 1079 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); 1080 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; 1081 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); 1082 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; 1083 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); 1084 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; 1085 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); 1086 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; 1087 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); 1088 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; 1089 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); 1090 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; 1091 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); 1092 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; 1093 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); 1094 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; 1095 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); 1096 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; 1097 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); 1098 1099 if (sregs.u.e.features & KVM_SREGS_E_SPE) { 1100 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; 1101 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); 1102 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; 1103 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33); 1104 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; 1105 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34); 1106 } 1107 1108 if (sregs.u.e.features & KVM_SREGS_E_PM) { 1109 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; 1110 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35); 1111 } 1112 1113 if (sregs.u.e.features & KVM_SREGS_E_PC) { 1114 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; 1115 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36); 1116 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; 1117 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37); 1118 } 1119 } 1120 1121 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { 1122 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; 1123 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; 1124 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; 1125 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; 1126 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; 1127 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; 1128 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; 1129 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; 1130 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; 1131 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; 1132 } 1133 1134 if (sregs.u.e.features & KVM_SREGS_EXP) { 1135 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; 1136 } 1137 1138 if (sregs.u.e.features & KVM_SREGS_E_PD) { 1139 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; 1140 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; 1141 } 1142 1143 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { 1144 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; 1145 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; 1146 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; 1147 1148 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { 1149 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; 1150 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; 1151 } 1152 } 1153 1154 return 0; 1155 } 1156 1157 static int kvmppc_get_books_sregs(PowerPCCPU *cpu) 1158 { 1159 CPUPPCState *env = &cpu->env; 1160 struct kvm_sregs sregs; 1161 int ret; 1162 int i; 1163 1164 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1165 if (ret < 0) { 1166 return ret; 1167 } 1168 1169 if (!cpu->vhyp) { 1170 ppc_store_sdr1(env, sregs.u.s.sdr1); 1171 } 1172 1173 /* Sync SLB */ 1174 #ifdef TARGET_PPC64 1175 /* 1176 * The packed SLB array we get from KVM_GET_SREGS only contains 1177 * information about valid entries. So we flush our internal copy 1178 * to get rid of stale ones, then put all valid SLB entries back 1179 * in. 1180 */ 1181 memset(env->slb, 0, sizeof(env->slb)); 1182 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 1183 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe; 1184 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv; 1185 /* 1186 * Only restore valid entries 1187 */ 1188 if (rb & SLB_ESID_V) { 1189 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs); 1190 } 1191 } 1192 #endif 1193 1194 /* Sync SRs */ 1195 for (i = 0; i < 16; i++) { 1196 env->sr[i] = sregs.u.s.ppc32.sr[i]; 1197 } 1198 1199 /* Sync BATs */ 1200 for (i = 0; i < 8; i++) { 1201 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; 1202 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; 1203 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; 1204 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; 1205 } 1206 1207 return 0; 1208 } 1209 1210 int kvm_arch_get_registers(CPUState *cs, Error **errp) 1211 { 1212 PowerPCCPU *cpu = POWERPC_CPU(cs); 1213 CPUPPCState *env = &cpu->env; 1214 struct kvm_regs regs; 1215 int i, ret; 1216 1217 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1218 if (ret < 0) { 1219 return ret; 1220 } 1221 1222 ppc_set_cr(env, regs.cr); 1223 env->ctr = regs.ctr; 1224 env->lr = regs.lr; 1225 cpu_write_xer(env, regs.xer); 1226 env->msr = regs.msr; 1227 env->nip = regs.pc; 1228 1229 env->spr[SPR_SRR0] = regs.srr0; 1230 env->spr[SPR_SRR1] = regs.srr1; 1231 1232 env->spr[SPR_SPRG0] = regs.sprg0; 1233 env->spr[SPR_SPRG1] = regs.sprg1; 1234 env->spr[SPR_SPRG2] = regs.sprg2; 1235 env->spr[SPR_SPRG3] = regs.sprg3; 1236 env->spr[SPR_SPRG4] = regs.sprg4; 1237 env->spr[SPR_SPRG5] = regs.sprg5; 1238 env->spr[SPR_SPRG6] = regs.sprg6; 1239 env->spr[SPR_SPRG7] = regs.sprg7; 1240 1241 env->spr[SPR_BOOKE_PID] = regs.pid; 1242 1243 for (i = 0; i < 32; i++) { 1244 env->gpr[i] = regs.gpr[i]; 1245 } 1246 1247 kvm_get_fp(cs); 1248 1249 if (cap_booke_sregs) { 1250 ret = kvmppc_get_booke_sregs(cpu); 1251 if (ret < 0) { 1252 return ret; 1253 } 1254 } 1255 1256 if (cap_segstate) { 1257 ret = kvmppc_get_books_sregs(cpu); 1258 if (ret < 0) { 1259 return ret; 1260 } 1261 } 1262 1263 if (cap_hior) { 1264 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 1265 } 1266 1267 if (cap_one_reg) { 1268 /* 1269 * We deliberately ignore errors here, for kernels which have 1270 * the ONE_REG calls, but don't support the specific 1271 * registers, there's a reasonable chance things will still 1272 * work, at least until we try to migrate. 1273 */ 1274 for (i = 0; i < 1024; i++) { 1275 uint64_t id = env->spr_cb[i].one_reg_id; 1276 1277 if (id != 0) { 1278 kvm_get_one_spr(cs, id, i); 1279 } 1280 } 1281 1282 #ifdef TARGET_PPC64 1283 if (FIELD_EX64(env->msr, MSR, TS)) { 1284 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 1285 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 1286 } 1287 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 1288 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 1289 } 1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 1295 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 1296 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 1297 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 1298 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 1299 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 1300 } 1301 1302 if (cap_papr) { 1303 if (kvm_get_vpa(cs) < 0) { 1304 trace_kvm_failed_get_vpa(); 1305 } 1306 } 1307 1308 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1309 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 1310 #endif 1311 } 1312 1313 return 0; 1314 } 1315 1316 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) 1317 { 1318 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; 1319 1320 if (irq != PPC_INTERRUPT_EXT) { 1321 return 0; 1322 } 1323 1324 if (!cap_interrupt_unset) { 1325 return 0; 1326 } 1327 1328 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1329 1330 return 0; 1331 } 1332 1333 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1334 { 1335 } 1336 1337 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1338 { 1339 return MEMTXATTRS_UNSPECIFIED; 1340 } 1341 1342 int kvm_arch_process_async_events(CPUState *cs) 1343 { 1344 return cs->halted; 1345 } 1346 1347 static int kvmppc_handle_halt(PowerPCCPU *cpu) 1348 { 1349 CPUState *cs = CPU(cpu); 1350 CPUPPCState *env = &cpu->env; 1351 1352 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && 1353 FIELD_EX64(env->msr, MSR, EE)) { 1354 cs->halted = 1; 1355 cs->exception_index = EXCP_HLT; 1356 } 1357 1358 return 0; 1359 } 1360 1361 /* map dcr access to existing qemu dcr emulation */ 1362 static int kvmppc_handle_dcr_read(CPUPPCState *env, 1363 uint32_t dcrn, uint32_t *data) 1364 { 1365 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) { 1366 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int kvmppc_handle_dcr_write(CPUPPCState *env, 1373 uint32_t dcrn, uint32_t data) 1374 { 1375 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) { 1376 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); 1377 } 1378 1379 return 0; 1380 } 1381 1382 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1383 { 1384 /* Mixed endian case is not handled */ 1385 uint32_t sc = debug_inst_opcode; 1386 1387 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1388 sizeof(sc), 0) || 1389 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) { 1390 return -EINVAL; 1391 } 1392 1393 return 0; 1394 } 1395 1396 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1397 { 1398 uint32_t sc; 1399 1400 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) || 1401 sc != debug_inst_opcode || 1402 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1403 sizeof(sc), 1)) { 1404 return -EINVAL; 1405 } 1406 1407 return 0; 1408 } 1409 1410 static int find_hw_breakpoint(target_ulong addr, int type) 1411 { 1412 int n; 1413 1414 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1415 <= ARRAY_SIZE(hw_debug_points)); 1416 1417 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1418 if (hw_debug_points[n].addr == addr && 1419 hw_debug_points[n].type == type) { 1420 return n; 1421 } 1422 } 1423 1424 return -1; 1425 } 1426 1427 static int find_hw_watchpoint(target_ulong addr, int *flag) 1428 { 1429 int n; 1430 1431 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS); 1432 if (n >= 0) { 1433 *flag = BP_MEM_ACCESS; 1434 return n; 1435 } 1436 1437 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE); 1438 if (n >= 0) { 1439 *flag = BP_MEM_WRITE; 1440 return n; 1441 } 1442 1443 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ); 1444 if (n >= 0) { 1445 *flag = BP_MEM_READ; 1446 return n; 1447 } 1448 1449 return -1; 1450 } 1451 1452 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 1453 { 1454 const unsigned breakpoint_index = nb_hw_breakpoint + nb_hw_watchpoint; 1455 if (breakpoint_index >= ARRAY_SIZE(hw_debug_points)) { 1456 return -ENOBUFS; 1457 } 1458 1459 hw_debug_points[breakpoint_index].addr = addr; 1460 hw_debug_points[breakpoint_index].type = type; 1461 1462 switch (type) { 1463 case GDB_BREAKPOINT_HW: 1464 if (nb_hw_breakpoint >= max_hw_breakpoint) { 1465 return -ENOBUFS; 1466 } 1467 1468 if (find_hw_breakpoint(addr, type) >= 0) { 1469 return -EEXIST; 1470 } 1471 1472 nb_hw_breakpoint++; 1473 break; 1474 1475 case GDB_WATCHPOINT_WRITE: 1476 case GDB_WATCHPOINT_READ: 1477 case GDB_WATCHPOINT_ACCESS: 1478 if (nb_hw_watchpoint >= max_hw_watchpoint) { 1479 return -ENOBUFS; 1480 } 1481 1482 if (find_hw_breakpoint(addr, type) >= 0) { 1483 return -EEXIST; 1484 } 1485 1486 nb_hw_watchpoint++; 1487 break; 1488 1489 default: 1490 return -ENOSYS; 1491 } 1492 1493 return 0; 1494 } 1495 1496 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 1497 { 1498 int n; 1499 1500 n = find_hw_breakpoint(addr, type); 1501 if (n < 0) { 1502 return -ENOENT; 1503 } 1504 1505 switch (type) { 1506 case GDB_BREAKPOINT_HW: 1507 nb_hw_breakpoint--; 1508 break; 1509 1510 case GDB_WATCHPOINT_WRITE: 1511 case GDB_WATCHPOINT_READ: 1512 case GDB_WATCHPOINT_ACCESS: 1513 nb_hw_watchpoint--; 1514 break; 1515 1516 default: 1517 return -ENOSYS; 1518 } 1519 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint]; 1520 1521 return 0; 1522 } 1523 1524 void kvm_arch_remove_all_hw_breakpoints(void) 1525 { 1526 nb_hw_breakpoint = nb_hw_watchpoint = 0; 1527 } 1528 1529 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1530 { 1531 int n; 1532 1533 /* Software Breakpoint updates */ 1534 if (kvm_sw_breakpoints_active(cs)) { 1535 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1536 } 1537 1538 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1539 <= ARRAY_SIZE(hw_debug_points)); 1540 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp)); 1541 1542 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1543 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; 1544 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp)); 1545 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1546 switch (hw_debug_points[n].type) { 1547 case GDB_BREAKPOINT_HW: 1548 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT; 1549 break; 1550 case GDB_WATCHPOINT_WRITE: 1551 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE; 1552 break; 1553 case GDB_WATCHPOINT_READ: 1554 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ; 1555 break; 1556 case GDB_WATCHPOINT_ACCESS: 1557 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE | 1558 KVMPPC_DEBUG_WATCH_READ; 1559 break; 1560 default: 1561 cpu_abort(cs, "Unsupported breakpoint type\n"); 1562 } 1563 dbg->arch.bp[n].addr = hw_debug_points[n].addr; 1564 } 1565 } 1566 } 1567 1568 static int kvm_handle_hw_breakpoint(CPUState *cs, 1569 struct kvm_debug_exit_arch *arch_info) 1570 { 1571 int handle = DEBUG_RETURN_GUEST; 1572 int n; 1573 int flag = 0; 1574 1575 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1576 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) { 1577 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW); 1578 if (n >= 0) { 1579 handle = DEBUG_RETURN_GDB; 1580 } 1581 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ | 1582 KVMPPC_DEBUG_WATCH_WRITE)) { 1583 n = find_hw_watchpoint(arch_info->address, &flag); 1584 if (n >= 0) { 1585 handle = DEBUG_RETURN_GDB; 1586 cs->watchpoint_hit = &hw_watchpoint; 1587 hw_watchpoint.vaddr = hw_debug_points[n].addr; 1588 hw_watchpoint.flags = flag; 1589 } 1590 } 1591 } 1592 return handle; 1593 } 1594 1595 static int kvm_handle_singlestep(void) 1596 { 1597 return DEBUG_RETURN_GDB; 1598 } 1599 1600 static int kvm_handle_sw_breakpoint(void) 1601 { 1602 return DEBUG_RETURN_GDB; 1603 } 1604 1605 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) 1606 { 1607 CPUState *cs = CPU(cpu); 1608 CPUPPCState *env = &cpu->env; 1609 struct kvm_debug_exit_arch *arch_info = &run->debug.arch; 1610 1611 if (cs->singlestep_enabled) { 1612 return kvm_handle_singlestep(); 1613 } 1614 1615 if (arch_info->status) { 1616 return kvm_handle_hw_breakpoint(cs, arch_info); 1617 } 1618 1619 if (kvm_find_sw_breakpoint(cs, arch_info->address)) { 1620 return kvm_handle_sw_breakpoint(); 1621 } 1622 1623 /* 1624 * QEMU is not able to handle debug exception, so inject 1625 * program exception to guest; 1626 * Yes program exception NOT debug exception !! 1627 * When QEMU is using debug resources then debug exception must 1628 * be always set. To achieve this we set MSR_DE and also set 1629 * MSRP_DEP so guest cannot change MSR_DE. 1630 * When emulating debug resource for guest we want guest 1631 * to control MSR_DE (enable/disable debug interrupt on need). 1632 * Supporting both configurations are NOT possible. 1633 * So the result is that we cannot share debug resources 1634 * between QEMU and Guest on BOOKE architecture. 1635 * In the current design QEMU gets the priority over guest, 1636 * this means that if QEMU is using debug resources then guest 1637 * cannot use them; 1638 * For software breakpoint QEMU uses a privileged instruction; 1639 * So there cannot be any reason that we are here for guest 1640 * set debug exception, only possibility is guest executed a 1641 * privileged / illegal instruction and that's why we are 1642 * injecting a program interrupt. 1643 */ 1644 cpu_synchronize_state(cs); 1645 /* 1646 * env->nip is PC, so increment this by 4 to use 1647 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4. 1648 */ 1649 env->nip += 4; 1650 cs->exception_index = POWERPC_EXCP_PROGRAM; 1651 env->error_code = POWERPC_EXCP_INVAL; 1652 ppc_cpu_do_interrupt(cs); 1653 1654 return DEBUG_RETURN_GUEST; 1655 } 1656 1657 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1658 { 1659 PowerPCCPU *cpu = POWERPC_CPU(cs); 1660 CPUPPCState *env = &cpu->env; 1661 int ret; 1662 1663 bql_lock(); 1664 1665 switch (run->exit_reason) { 1666 case KVM_EXIT_DCR: 1667 if (run->dcr.is_write) { 1668 trace_kvm_handle_dcr_write(); 1669 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); 1670 } else { 1671 trace_kvm_handle_dcr_read(); 1672 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); 1673 } 1674 break; 1675 case KVM_EXIT_HLT: 1676 trace_kvm_handle_halt(); 1677 ret = kvmppc_handle_halt(cpu); 1678 break; 1679 #if defined(CONFIG_PSERIES) 1680 case KVM_EXIT_PAPR_HCALL: 1681 trace_kvm_handle_papr_hcall(run->papr_hcall.nr); 1682 run->papr_hcall.ret = spapr_hypercall(cpu, 1683 run->papr_hcall.nr, 1684 run->papr_hcall.args); 1685 ret = 0; 1686 break; 1687 #endif 1688 case KVM_EXIT_EPR: 1689 trace_kvm_handle_epr(); 1690 run->epr.epr = ldl_phys(cs->as, env->mpic_iack); 1691 ret = 0; 1692 break; 1693 case KVM_EXIT_WATCHDOG: 1694 trace_kvm_handle_watchdog_expiry(); 1695 watchdog_perform_action(); 1696 ret = 0; 1697 break; 1698 1699 case KVM_EXIT_DEBUG: 1700 trace_kvm_handle_debug_exception(); 1701 if (kvm_handle_debug(cpu, run)) { 1702 ret = EXCP_DEBUG; 1703 break; 1704 } 1705 /* re-enter, this exception was guest-internal */ 1706 ret = 0; 1707 break; 1708 1709 #if defined(CONFIG_PSERIES) 1710 case KVM_EXIT_NMI: 1711 trace_kvm_handle_nmi_exception(); 1712 ret = kvm_handle_nmi(cpu, run); 1713 break; 1714 #endif 1715 1716 default: 1717 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); 1718 ret = -1; 1719 break; 1720 } 1721 1722 bql_unlock(); 1723 return ret; 1724 } 1725 1726 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1727 { 1728 CPUState *cs = CPU(cpu); 1729 uint32_t bits = tsr_bits; 1730 struct kvm_one_reg reg = { 1731 .id = KVM_REG_PPC_OR_TSR, 1732 .addr = (uintptr_t) &bits, 1733 }; 1734 1735 if (!kvm_enabled()) { 1736 return 0; 1737 } 1738 1739 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1740 } 1741 1742 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1743 { 1744 1745 CPUState *cs = CPU(cpu); 1746 uint32_t bits = tsr_bits; 1747 struct kvm_one_reg reg = { 1748 .id = KVM_REG_PPC_CLEAR_TSR, 1749 .addr = (uintptr_t) &bits, 1750 }; 1751 1752 if (!kvm_enabled()) { 1753 return 0; 1754 } 1755 1756 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1757 } 1758 1759 int kvmppc_set_tcr(PowerPCCPU *cpu) 1760 { 1761 CPUState *cs = CPU(cpu); 1762 CPUPPCState *env = &cpu->env; 1763 uint32_t tcr = env->spr[SPR_BOOKE_TCR]; 1764 1765 struct kvm_one_reg reg = { 1766 .id = KVM_REG_PPC_TCR, 1767 .addr = (uintptr_t) &tcr, 1768 }; 1769 1770 if (!kvm_enabled()) { 1771 return 0; 1772 } 1773 1774 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1775 } 1776 1777 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) 1778 { 1779 CPUState *cs = CPU(cpu); 1780 int ret; 1781 1782 if (!kvm_enabled()) { 1783 return -1; 1784 } 1785 1786 if (!cap_ppc_watchdog) { 1787 printf("warning: KVM does not support watchdog"); 1788 return -1; 1789 } 1790 1791 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0); 1792 if (ret < 0) { 1793 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", 1794 __func__, strerror(-ret)); 1795 return ret; 1796 } 1797 1798 return ret; 1799 } 1800 1801 static int read_cpuinfo(const char *field, char *value, int len) 1802 { 1803 FILE *f; 1804 int ret = -1; 1805 int field_len = strlen(field); 1806 char line[512]; 1807 1808 f = fopen("/proc/cpuinfo", "r"); 1809 if (!f) { 1810 return -1; 1811 } 1812 1813 do { 1814 if (!fgets(line, sizeof(line), f)) { 1815 break; 1816 } 1817 if (!strncmp(line, field, field_len)) { 1818 pstrcpy(value, len, line); 1819 ret = 0; 1820 break; 1821 } 1822 } while (*line); 1823 1824 fclose(f); 1825 1826 return ret; 1827 } 1828 1829 static uint32_t kvmppc_get_tbfreq_procfs(void) 1830 { 1831 char line[512]; 1832 char *ns; 1833 uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND; 1834 uint32_t tbfreq_procfs; 1835 1836 if (read_cpuinfo("timebase", line, sizeof(line))) { 1837 return tbfreq_fallback; 1838 } 1839 1840 ns = strchr(line, ':'); 1841 if (!ns) { 1842 return tbfreq_fallback; 1843 } 1844 1845 tbfreq_procfs = atoi(++ns); 1846 1847 /* 0 is certainly not acceptable by the guest, return fallback value */ 1848 return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback; 1849 } 1850 1851 uint32_t kvmppc_get_tbfreq(void) 1852 { 1853 static uint32_t cached_tbfreq; 1854 1855 if (!cached_tbfreq) { 1856 cached_tbfreq = kvmppc_get_tbfreq_procfs(); 1857 } 1858 1859 return cached_tbfreq; 1860 } 1861 1862 bool kvmppc_get_host_serial(char **value) 1863 { 1864 return g_file_get_contents("/proc/device-tree/system-id", value, NULL, 1865 NULL); 1866 } 1867 1868 bool kvmppc_get_host_model(char **value) 1869 { 1870 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL); 1871 } 1872 1873 /* Try to find a device tree node for a CPU with clock-frequency property */ 1874 static int kvmppc_find_cpu_dt(char *buf, int buf_len) 1875 { 1876 struct dirent *dirp; 1877 DIR *dp; 1878 1879 dp = opendir(PROC_DEVTREE_CPU); 1880 if (!dp) { 1881 printf("Can't open directory " PROC_DEVTREE_CPU "\n"); 1882 return -1; 1883 } 1884 1885 buf[0] = '\0'; 1886 while ((dirp = readdir(dp)) != NULL) { 1887 FILE *f; 1888 1889 /* Don't accidentally read from the current and parent directories */ 1890 if (strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0) { 1891 continue; 1892 } 1893 1894 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, 1895 dirp->d_name); 1896 f = fopen(buf, "r"); 1897 if (f) { 1898 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); 1899 fclose(f); 1900 break; 1901 } 1902 buf[0] = '\0'; 1903 } 1904 closedir(dp); 1905 if (buf[0] == '\0') { 1906 printf("Unknown host!\n"); 1907 return -1; 1908 } 1909 1910 return 0; 1911 } 1912 1913 static uint64_t kvmppc_read_int_dt(const char *filename) 1914 { 1915 union { 1916 uint32_t v32; 1917 uint64_t v64; 1918 } u; 1919 FILE *f; 1920 int len; 1921 1922 f = fopen(filename, "rb"); 1923 if (!f) { 1924 return -1; 1925 } 1926 1927 len = fread(&u, 1, sizeof(u), f); 1928 fclose(f); 1929 switch (len) { 1930 case 4: 1931 /* property is a 32-bit quantity */ 1932 return be32_to_cpu(u.v32); 1933 case 8: 1934 return be64_to_cpu(u.v64); 1935 } 1936 1937 return 0; 1938 } 1939 1940 /* 1941 * Read a CPU node property from the host device tree that's a single 1942 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong 1943 * (can't find or open the property, or doesn't understand the format) 1944 */ 1945 static uint64_t kvmppc_read_int_cpu_dt(const char *propname) 1946 { 1947 char buf[PATH_MAX], *tmp; 1948 uint64_t val; 1949 1950 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { 1951 return -1; 1952 } 1953 1954 tmp = g_strdup_printf("%s/%s", buf, propname); 1955 val = kvmppc_read_int_dt(tmp); 1956 g_free(tmp); 1957 1958 return val; 1959 } 1960 1961 uint64_t kvmppc_get_clockfreq(void) 1962 { 1963 return kvmppc_read_int_cpu_dt("clock-frequency"); 1964 } 1965 1966 static int kvmppc_get_dec_bits(void) 1967 { 1968 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits"); 1969 1970 if (nr_bits > 0) { 1971 return nr_bits; 1972 } 1973 return 0; 1974 } 1975 1976 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) 1977 { 1978 CPUState *cs = env_cpu(env); 1979 1980 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && 1981 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { 1982 return 0; 1983 } 1984 1985 return 1; 1986 } 1987 1988 int kvmppc_get_hasidle(CPUPPCState *env) 1989 { 1990 struct kvm_ppc_pvinfo pvinfo; 1991 1992 if (!kvmppc_get_pvinfo(env, &pvinfo) && 1993 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { 1994 return 1; 1995 } 1996 1997 return 0; 1998 } 1999 2000 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) 2001 { 2002 uint32_t *hc = (uint32_t *)buf; 2003 struct kvm_ppc_pvinfo pvinfo; 2004 2005 if (!kvmppc_get_pvinfo(env, &pvinfo)) { 2006 memcpy(buf, pvinfo.hcall, buf_len); 2007 return 0; 2008 } 2009 2010 /* 2011 * Fallback to always fail hypercalls regardless of endianness: 2012 * 2013 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian) 2014 * li r3, -1 2015 * b .+8 (becomes nop in wrong endian) 2016 * bswap32(li r3, -1) 2017 */ 2018 2019 hc[0] = cpu_to_be32(0x08000048); 2020 hc[1] = cpu_to_be32(0x3860ffff); 2021 hc[2] = cpu_to_be32(0x48000008); 2022 hc[3] = cpu_to_be32(bswap32(0x3860ffff)); 2023 2024 return 1; 2025 } 2026 2027 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall) 2028 { 2029 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1); 2030 } 2031 2032 void kvmppc_enable_logical_ci_hcalls(void) 2033 { 2034 /* 2035 * FIXME: it would be nice if we could detect the cases where 2036 * we're using a device which requires the in kernel 2037 * implementation of these hcalls, but the kernel lacks them and 2038 * produce a warning. 2039 */ 2040 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD); 2041 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE); 2042 } 2043 2044 void kvmppc_enable_set_mode_hcall(void) 2045 { 2046 kvmppc_enable_hcall(kvm_state, H_SET_MODE); 2047 } 2048 2049 void kvmppc_enable_clear_ref_mod_hcalls(void) 2050 { 2051 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF); 2052 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD); 2053 } 2054 2055 void kvmppc_enable_h_page_init(void) 2056 { 2057 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT); 2058 } 2059 2060 void kvmppc_enable_h_rpt_invalidate(void) 2061 { 2062 kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE); 2063 } 2064 2065 #ifdef CONFIG_PSERIES 2066 void kvmppc_set_papr(PowerPCCPU *cpu) 2067 { 2068 CPUState *cs = CPU(cpu); 2069 int ret; 2070 2071 if (!kvm_enabled()) { 2072 return; 2073 } 2074 2075 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0); 2076 if (ret) { 2077 error_report("This vCPU type or KVM version does not support PAPR"); 2078 exit(1); 2079 } 2080 2081 /* 2082 * Update the capability flag so we sync the right information 2083 * with kvm 2084 */ 2085 cap_papr = 1; 2086 } 2087 #endif 2088 2089 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr) 2090 { 2091 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr); 2092 } 2093 2094 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) 2095 { 2096 CPUState *cs = CPU(cpu); 2097 int ret; 2098 2099 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy); 2100 if (ret && mpic_proxy) { 2101 error_report("This KVM version does not support EPR"); 2102 exit(1); 2103 } 2104 } 2105 2106 bool kvmppc_get_fwnmi(void) 2107 { 2108 return cap_fwnmi; 2109 } 2110 2111 int kvmppc_set_fwnmi(PowerPCCPU *cpu) 2112 { 2113 CPUState *cs = CPU(cpu); 2114 2115 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); 2116 } 2117 2118 bool kvmppc_has_cap_dawr1(void) 2119 { 2120 return !!cap_dawr1; 2121 } 2122 2123 int kvmppc_set_cap_dawr1(int enable) 2124 { 2125 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_DAWR1, 0, enable); 2126 } 2127 2128 int kvmppc_smt_threads(void) 2129 { 2130 return cap_ppc_smt ? cap_ppc_smt : 1; 2131 } 2132 2133 int kvmppc_set_smt_threads(int smt) 2134 { 2135 int ret; 2136 2137 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0); 2138 if (!ret) { 2139 cap_ppc_smt = smt; 2140 } 2141 return ret; 2142 } 2143 2144 void kvmppc_error_append_smt_possible_hint(Error *const *errp) 2145 { 2146 int i; 2147 GString *g; 2148 char *s; 2149 2150 assert(kvm_enabled()); 2151 if (cap_ppc_smt_possible) { 2152 g = g_string_new("Available VSMT modes:"); 2153 for (i = 63; i >= 0; i--) { 2154 if ((1UL << i) & cap_ppc_smt_possible) { 2155 g_string_append_printf(g, " %lu", (1UL << i)); 2156 } 2157 } 2158 s = g_string_free(g, false); 2159 error_append_hint(errp, "%s.\n", s); 2160 g_free(s); 2161 } else { 2162 error_append_hint(errp, 2163 "This KVM seems to be too old to support VSMT.\n"); 2164 } 2165 } 2166 2167 2168 #ifdef TARGET_PPC64 2169 uint64_t kvmppc_vrma_limit(unsigned int hash_shift) 2170 { 2171 struct kvm_ppc_smmu_info info; 2172 long rampagesize, best_page_shift; 2173 int i; 2174 2175 /* 2176 * Find the largest hardware supported page size that's less than 2177 * or equal to the (logical) backing page size of guest RAM 2178 */ 2179 kvm_get_smmu_info(&info, &error_fatal); 2180 rampagesize = qemu_minrampagesize(); 2181 best_page_shift = 0; 2182 2183 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { 2184 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i]; 2185 2186 if (!sps->page_shift) { 2187 continue; 2188 } 2189 2190 if ((sps->page_shift > best_page_shift) 2191 && ((1UL << sps->page_shift) <= rampagesize)) { 2192 best_page_shift = sps->page_shift; 2193 } 2194 } 2195 2196 return 1ULL << (best_page_shift + hash_shift - 7); 2197 } 2198 #endif 2199 2200 bool kvmppc_spapr_use_multitce(void) 2201 { 2202 return cap_spapr_multitce; 2203 } 2204 2205 int kvmppc_spapr_enable_inkernel_multitce(void) 2206 { 2207 int ret; 2208 2209 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2210 H_PUT_TCE_INDIRECT, 1); 2211 if (!ret) { 2212 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2213 H_STUFF_TCE, 1); 2214 } 2215 2216 return ret; 2217 } 2218 2219 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift, 2220 uint64_t bus_offset, uint32_t nb_table, 2221 int *pfd, bool need_vfio) 2222 { 2223 long len; 2224 int fd; 2225 void *table; 2226 2227 /* 2228 * Must set fd to -1 so we don't try to munmap when called for 2229 * destroying the table, which the upper layers -will- do 2230 */ 2231 *pfd = -1; 2232 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) { 2233 return NULL; 2234 } 2235 2236 if (cap_spapr_tce_64) { 2237 struct kvm_create_spapr_tce_64 args = { 2238 .liobn = liobn, 2239 .page_shift = page_shift, 2240 .offset = bus_offset >> page_shift, 2241 .size = nb_table, 2242 .flags = 0 2243 }; 2244 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args); 2245 if (fd < 0) { 2246 fprintf(stderr, 2247 "KVM: Failed to create TCE64 table for liobn 0x%x\n", 2248 liobn); 2249 return NULL; 2250 } 2251 } else if (cap_spapr_tce) { 2252 uint64_t window_size = (uint64_t) nb_table << page_shift; 2253 struct kvm_create_spapr_tce args = { 2254 .liobn = liobn, 2255 .window_size = window_size, 2256 }; 2257 if ((window_size != args.window_size) || bus_offset) { 2258 return NULL; 2259 } 2260 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); 2261 if (fd < 0) { 2262 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n", 2263 liobn); 2264 return NULL; 2265 } 2266 } else { 2267 return NULL; 2268 } 2269 2270 len = nb_table * sizeof(uint64_t); 2271 /* FIXME: round this up to page size */ 2272 2273 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); 2274 if (table == MAP_FAILED) { 2275 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n", 2276 liobn); 2277 close(fd); 2278 return NULL; 2279 } 2280 2281 *pfd = fd; 2282 return table; 2283 } 2284 2285 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table) 2286 { 2287 long len; 2288 2289 if (fd < 0) { 2290 return -1; 2291 } 2292 2293 len = nb_table * sizeof(uint64_t); 2294 if ((munmap(table, len) < 0) || 2295 (close(fd) < 0)) { 2296 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", 2297 strerror(errno)); 2298 /* Leak the table */ 2299 } 2300 2301 return 0; 2302 } 2303 2304 int kvmppc_reset_htab(int shift_hint) 2305 { 2306 uint32_t shift = shift_hint; 2307 2308 if (!kvm_enabled()) { 2309 /* Full emulation, tell caller to allocate htab itself */ 2310 return 0; 2311 } 2312 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) { 2313 int ret; 2314 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); 2315 if (ret == -ENOTTY) { 2316 /* 2317 * At least some versions of PR KVM advertise the 2318 * capability, but don't implement the ioctl(). Oops. 2319 * Return 0 so that we allocate the htab in qemu, as is 2320 * correct for PR. 2321 */ 2322 return 0; 2323 } else if (ret < 0) { 2324 return ret; 2325 } 2326 return shift; 2327 } 2328 2329 /* 2330 * We have a kernel that predates the htab reset calls. For PR 2331 * KVM, we need to allocate the htab ourselves, for an HV KVM of 2332 * this era, it has allocated a 16MB fixed size hash table 2333 * already. 2334 */ 2335 if (kvmppc_is_pr(kvm_state)) { 2336 /* PR - tell caller to allocate htab */ 2337 return 0; 2338 } else { 2339 /* HV - assume 16MB kernel allocated htab */ 2340 return 24; 2341 } 2342 } 2343 2344 static inline uint32_t mfpvr(void) 2345 { 2346 uint32_t pvr; 2347 2348 asm ("mfpvr %0" 2349 : "=r"(pvr)); 2350 return pvr; 2351 } 2352 2353 static void alter_insns(uint64_t *word, uint64_t flags, bool on) 2354 { 2355 if (on) { 2356 *word |= flags; 2357 } else { 2358 *word &= ~flags; 2359 } 2360 } 2361 2362 static bool kvmppc_cpu_realize(CPUState *cs, Error **errp) 2363 { 2364 int ret; 2365 const char *vcpu_str = (cs->parent_obj.hotplugged == true) ? 2366 "hotplug" : "create"; 2367 cs->cpu_index = cpu_get_free_index(); 2368 2369 POWERPC_CPU(cs)->vcpu_id = cs->cpu_index; 2370 2371 /* create and park to fail gracefully in case vcpu hotplug fails */ 2372 ret = kvm_create_and_park_vcpu(cs); 2373 if (ret) { 2374 /* 2375 * This causes QEMU to terminate if initial CPU creation 2376 * fails, and only CPU hotplug failure if the error happens 2377 * there. 2378 */ 2379 error_setg(errp, "%s: vcpu %s failed with %d", 2380 __func__, vcpu_str, ret); 2381 return false; 2382 } 2383 return true; 2384 } 2385 2386 static void kvmppc_host_cpu_class_init(ObjectClass *oc, const void *data) 2387 { 2388 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2389 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); 2390 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); 2391 2392 /* Now fix up the class with information we can query from the host */ 2393 pcc->pvr = mfpvr(); 2394 2395 alter_insns(&pcc->insns_flags, PPC_ALTIVEC, 2396 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC); 2397 alter_insns(&pcc->insns_flags2, PPC2_VSX, 2398 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX); 2399 alter_insns(&pcc->insns_flags2, PPC2_DFP, 2400 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP); 2401 2402 if (dcache_size != -1) { 2403 pcc->l1_dcache_size = dcache_size; 2404 } 2405 2406 if (icache_size != -1) { 2407 pcc->l1_icache_size = icache_size; 2408 } 2409 2410 #if defined(TARGET_PPC64) 2411 pcc->radix_page_info = kvmppc_get_radix_page_info(); 2412 #endif /* defined(TARGET_PPC64) */ 2413 } 2414 2415 bool kvmppc_has_cap_epr(void) 2416 { 2417 return cap_epr; 2418 } 2419 2420 bool kvmppc_has_cap_fixup_hcalls(void) 2421 { 2422 return cap_fixup_hcalls; 2423 } 2424 2425 bool kvmppc_has_cap_htm(void) 2426 { 2427 return cap_htm; 2428 } 2429 2430 bool kvmppc_has_cap_mmu_radix(void) 2431 { 2432 return cap_mmu_radix; 2433 } 2434 2435 bool kvmppc_has_cap_mmu_hash_v3(void) 2436 { 2437 return cap_mmu_hash_v3; 2438 } 2439 2440 static bool kvmppc_power8_host(void) 2441 { 2442 bool ret = false; 2443 #ifdef TARGET_PPC64 2444 { 2445 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); 2446 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || 2447 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || 2448 (base_pvr == CPU_POWERPC_POWER8_BASE); 2449 } 2450 #endif /* TARGET_PPC64 */ 2451 return ret; 2452 } 2453 2454 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) 2455 { 2456 bool l1d_thread_priv_req = !kvmppc_power8_host(); 2457 2458 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { 2459 return 2; 2460 } else if ((!l1d_thread_priv_req || 2461 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && 2462 (c.character & c.character_mask 2463 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { 2464 return 1; 2465 } 2466 2467 return 0; 2468 } 2469 2470 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c) 2471 { 2472 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) { 2473 return 2; 2474 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) { 2475 return 1; 2476 } 2477 2478 return 0; 2479 } 2480 2481 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c) 2482 { 2483 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) && 2484 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) && 2485 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) { 2486 return SPAPR_CAP_FIXED_NA; 2487 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) { 2488 return SPAPR_CAP_WORKAROUND; 2489 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) { 2490 return SPAPR_CAP_FIXED_CCD; 2491 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) { 2492 return SPAPR_CAP_FIXED_IBS; 2493 } 2494 2495 return 0; 2496 } 2497 2498 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c) 2499 { 2500 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) { 2501 return 1; 2502 } 2503 return 0; 2504 } 2505 2506 bool kvmppc_has_cap_xive(void) 2507 { 2508 return cap_xive; 2509 } 2510 2511 static void kvmppc_get_cpu_characteristics(KVMState *s) 2512 { 2513 struct kvm_ppc_cpu_char c; 2514 int ret; 2515 2516 /* Assume broken */ 2517 cap_ppc_safe_cache = 0; 2518 cap_ppc_safe_bounds_check = 0; 2519 cap_ppc_safe_indirect_branch = 0; 2520 2521 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR); 2522 if (!ret) { 2523 return; 2524 } 2525 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c); 2526 if (ret < 0) { 2527 return; 2528 } 2529 2530 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c); 2531 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c); 2532 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c); 2533 cap_ppc_count_cache_flush_assist = 2534 parse_cap_ppc_count_cache_flush_assist(c); 2535 } 2536 2537 int kvmppc_get_cap_safe_cache(void) 2538 { 2539 return cap_ppc_safe_cache; 2540 } 2541 2542 int kvmppc_get_cap_safe_bounds_check(void) 2543 { 2544 return cap_ppc_safe_bounds_check; 2545 } 2546 2547 int kvmppc_get_cap_safe_indirect_branch(void) 2548 { 2549 return cap_ppc_safe_indirect_branch; 2550 } 2551 2552 int kvmppc_get_cap_count_cache_flush_assist(void) 2553 { 2554 return cap_ppc_count_cache_flush_assist; 2555 } 2556 2557 bool kvmppc_has_cap_nested_kvm_hv(void) 2558 { 2559 return !!cap_ppc_nested_kvm_hv; 2560 } 2561 2562 int kvmppc_set_cap_nested_kvm_hv(int enable) 2563 { 2564 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable); 2565 } 2566 2567 bool kvmppc_has_cap_spapr_vfio(void) 2568 { 2569 return cap_spapr_vfio; 2570 } 2571 2572 int kvmppc_get_cap_large_decr(void) 2573 { 2574 return cap_large_decr; 2575 } 2576 2577 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable) 2578 { 2579 CPUState *cs = CPU(cpu); 2580 uint64_t lpcr = 0; 2581 2582 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2583 /* Do we need to modify the LPCR? */ 2584 if (!!(lpcr & LPCR_LD) != !!enable) { 2585 if (enable) { 2586 lpcr |= LPCR_LD; 2587 } else { 2588 lpcr &= ~LPCR_LD; 2589 } 2590 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2591 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2592 2593 if (!!(lpcr & LPCR_LD) != !!enable) { 2594 return -1; 2595 } 2596 } 2597 2598 return 0; 2599 } 2600 2601 int kvmppc_has_cap_rpt_invalidate(void) 2602 { 2603 return cap_rpt_invalidate; 2604 } 2605 2606 bool kvmppc_supports_ail_3(void) 2607 { 2608 return cap_ail_mode_3; 2609 } 2610 2611 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) 2612 { 2613 uint32_t host_pvr = mfpvr(); 2614 PowerPCCPUClass *pvr_pcc; 2615 2616 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); 2617 if (pvr_pcc == NULL) { 2618 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); 2619 } 2620 2621 return pvr_pcc; 2622 } 2623 2624 static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque) 2625 { 2626 MachineClass *mc = MACHINE_CLASS(oc); 2627 2628 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU; 2629 } 2630 2631 static int kvm_ppc_register_host_cpu_type(void) 2632 { 2633 TypeInfo type_info = { 2634 .name = TYPE_HOST_POWERPC_CPU, 2635 .class_init = kvmppc_host_cpu_class_init, 2636 }; 2637 PowerPCCPUClass *pvr_pcc; 2638 ObjectClass *oc; 2639 DeviceClass *dc; 2640 int i; 2641 2642 pvr_pcc = kvm_ppc_get_host_cpu_class(); 2643 if (pvr_pcc == NULL) { 2644 return -1; 2645 } 2646 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); 2647 type_register_static(&type_info); 2648 /* override TCG default cpu type with 'host' cpu model */ 2649 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE, 2650 false, NULL); 2651 2652 oc = object_class_by_name(type_info.name); 2653 g_assert(oc); 2654 2655 /* 2656 * Update generic CPU family class alias (e.g. on a POWER8NVL host, 2657 * we want "POWER8" to be a "family" alias that points to the current 2658 * host CPU type, too) 2659 */ 2660 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc)); 2661 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 2662 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) { 2663 char *suffix; 2664 2665 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc)); 2666 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX); 2667 if (suffix) { 2668 *suffix = 0; 2669 } 2670 break; 2671 } 2672 } 2673 2674 return 0; 2675 } 2676 2677 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function) 2678 { 2679 struct kvm_rtas_token_args args = { 2680 .token = token, 2681 }; 2682 2683 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) { 2684 return -ENOENT; 2685 } 2686 2687 strncpy(args.name, function, sizeof(args.name) - 1); 2688 2689 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args); 2690 } 2691 2692 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp) 2693 { 2694 struct kvm_get_htab_fd s = { 2695 .flags = write ? KVM_GET_HTAB_WRITE : 0, 2696 .start_index = index, 2697 }; 2698 int ret; 2699 2700 if (!cap_htab_fd) { 2701 error_setg(errp, "KVM version doesn't support %s the HPT", 2702 write ? "writing" : "reading"); 2703 return -ENOTSUP; 2704 } 2705 2706 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); 2707 if (ret < 0) { 2708 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s", 2709 write ? "writing" : "reading", write ? "to" : "from", 2710 strerror(errno)); 2711 return -errno; 2712 } 2713 2714 return ret; 2715 } 2716 2717 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) 2718 { 2719 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2720 g_autofree uint8_t *buf = g_malloc(bufsize); 2721 ssize_t rc; 2722 2723 do { 2724 rc = read(fd, buf, bufsize); 2725 if (rc < 0) { 2726 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", 2727 strerror(errno)); 2728 return rc; 2729 } else if (rc) { 2730 uint8_t *buffer = buf; 2731 ssize_t n = rc; 2732 while (n) { 2733 struct kvm_get_htab_header *head = 2734 (struct kvm_get_htab_header *) buffer; 2735 size_t chunksize = sizeof(*head) + 2736 HASH_PTE_SIZE_64 * head->n_valid; 2737 2738 qemu_put_be32(f, head->index); 2739 qemu_put_be16(f, head->n_valid); 2740 qemu_put_be16(f, head->n_invalid); 2741 qemu_put_buffer(f, (void *)(head + 1), 2742 HASH_PTE_SIZE_64 * head->n_valid); 2743 2744 buffer += chunksize; 2745 n -= chunksize; 2746 } 2747 } 2748 } while ((rc != 0) 2749 && ((max_ns < 0) || 2750 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns))); 2751 2752 return (rc == 0) ? 1 : 0; 2753 } 2754 2755 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, 2756 uint16_t n_valid, uint16_t n_invalid, Error **errp) 2757 { 2758 struct kvm_get_htab_header *buf; 2759 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64; 2760 ssize_t rc; 2761 2762 buf = alloca(chunksize); 2763 buf->index = index; 2764 buf->n_valid = n_valid; 2765 buf->n_invalid = n_invalid; 2766 2767 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid); 2768 2769 rc = write(fd, buf, chunksize); 2770 if (rc < 0) { 2771 error_setg_errno(errp, errno, "Error writing the KVM hash table"); 2772 return -errno; 2773 } 2774 if (rc != chunksize) { 2775 /* We should never get a short write on a single chunk */ 2776 error_setg(errp, "Short write while restoring the KVM hash table"); 2777 return -ENOSPC; 2778 } 2779 return 0; 2780 } 2781 2782 bool kvm_arch_stop_on_emulation_error(CPUState *cpu) 2783 { 2784 return true; 2785 } 2786 2787 void kvm_arch_init_irq_routing(KVMState *s) 2788 { 2789 } 2790 2791 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n) 2792 { 2793 int fd, rc; 2794 int i; 2795 2796 fd = kvmppc_get_htab_fd(false, ptex, &error_abort); 2797 2798 i = 0; 2799 while (i < n) { 2800 struct kvm_get_htab_header *hdr; 2801 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP; 2802 char buf[sizeof(*hdr) + HPTES_PER_GROUP * HASH_PTE_SIZE_64]; 2803 2804 rc = read(fd, buf, sizeof(*hdr) + m * HASH_PTE_SIZE_64); 2805 if (rc < 0) { 2806 hw_error("kvmppc_read_hptes: Unable to read HPTEs"); 2807 } 2808 2809 hdr = (struct kvm_get_htab_header *)buf; 2810 while ((i < n) && ((char *)hdr < (buf + rc))) { 2811 int invalid = hdr->n_invalid, valid = hdr->n_valid; 2812 2813 if (hdr->index != (ptex + i)) { 2814 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32 2815 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i); 2816 } 2817 2818 if (n - i < valid) { 2819 valid = n - i; 2820 } 2821 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid); 2822 i += valid; 2823 2824 if ((n - i) < invalid) { 2825 invalid = n - i; 2826 } 2827 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64); 2828 i += invalid; 2829 2830 hdr = (struct kvm_get_htab_header *) 2831 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid); 2832 } 2833 } 2834 2835 close(fd); 2836 } 2837 2838 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1) 2839 { 2840 int fd, rc; 2841 struct { 2842 struct kvm_get_htab_header hdr; 2843 uint64_t pte0; 2844 uint64_t pte1; 2845 } buf; 2846 2847 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort); 2848 2849 buf.hdr.n_valid = 1; 2850 buf.hdr.n_invalid = 0; 2851 buf.hdr.index = ptex; 2852 buf.pte0 = cpu_to_be64(pte0); 2853 buf.pte1 = cpu_to_be64(pte1); 2854 2855 rc = write(fd, &buf, sizeof(buf)); 2856 if (rc != sizeof(buf)) { 2857 hw_error("kvmppc_write_hpte: Unable to update KVM HPT"); 2858 } 2859 close(fd); 2860 } 2861 2862 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 2863 uint64_t address, uint32_t data, PCIDevice *dev) 2864 { 2865 return 0; 2866 } 2867 2868 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 2869 int vector, PCIDevice *dev) 2870 { 2871 return 0; 2872 } 2873 2874 int kvm_arch_release_virq_post(int virq) 2875 { 2876 return 0; 2877 } 2878 2879 int kvm_arch_msi_data_to_gsi(uint32_t data) 2880 { 2881 return data & 0xffff; 2882 } 2883 2884 #if defined(CONFIG_PSERIES) 2885 int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run) 2886 { 2887 uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK; 2888 2889 cpu_synchronize_state(CPU(cpu)); 2890 2891 spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV); 2892 2893 return 0; 2894 } 2895 #endif 2896 2897 int kvmppc_enable_hwrng(void) 2898 { 2899 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) { 2900 return -1; 2901 } 2902 2903 return kvmppc_enable_hcall(kvm_state, H_RANDOM); 2904 } 2905 2906 void kvmppc_check_papr_resize_hpt(Error **errp) 2907 { 2908 if (!kvm_enabled()) { 2909 return; /* No KVM, we're good */ 2910 } 2911 2912 if (cap_resize_hpt) { 2913 return; /* Kernel has explicit support, we're good */ 2914 } 2915 2916 /* Otherwise fallback on looking for PR KVM */ 2917 if (kvmppc_is_pr(kvm_state)) { 2918 return; 2919 } 2920 2921 error_setg(errp, 2922 "Hash page table resizing not available with this KVM version"); 2923 } 2924 2925 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift) 2926 { 2927 CPUState *cs = CPU(cpu); 2928 struct kvm_ppc_resize_hpt rhpt = { 2929 .flags = flags, 2930 .shift = shift, 2931 }; 2932 2933 if (!cap_resize_hpt) { 2934 return -ENOSYS; 2935 } 2936 2937 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt); 2938 } 2939 2940 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift) 2941 { 2942 CPUState *cs = CPU(cpu); 2943 struct kvm_ppc_resize_hpt rhpt = { 2944 .flags = flags, 2945 .shift = shift, 2946 }; 2947 2948 if (!cap_resize_hpt) { 2949 return -ENOSYS; 2950 } 2951 2952 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt); 2953 } 2954 2955 /* 2956 * This is a helper function to detect a post migration scenario 2957 * in which a guest, running as KVM-HV, freezes in cpu_post_load because 2958 * the guest kernel can't handle a PVR value other than the actual host 2959 * PVR in KVM_SET_SREGS, even if pvr_match() returns true. 2960 * 2961 * If we don't have cap_ppc_pvr_compat and we're not running in PR 2962 * (so, we're HV), return true. The workaround itself is done in 2963 * cpu_post_load. 2964 * 2965 * The order here is important: we'll only check for KVM PR as a 2966 * fallback if the guest kernel can't handle the situation itself. 2967 * We need to avoid as much as possible querying the running KVM type 2968 * in QEMU level. 2969 */ 2970 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu) 2971 { 2972 CPUState *cs = CPU(cpu); 2973 2974 if (!kvm_enabled()) { 2975 return false; 2976 } 2977 2978 if (cap_ppc_pvr_compat) { 2979 return false; 2980 } 2981 2982 return !kvmppc_is_pr(cs->kvm_state); 2983 } 2984 2985 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online) 2986 { 2987 CPUState *cs = CPU(cpu); 2988 2989 if (kvm_enabled()) { 2990 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online); 2991 } 2992 } 2993 2994 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset) 2995 { 2996 CPUState *cs = CPU(cpu); 2997 2998 if (kvm_enabled()) { 2999 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset); 3000 } 3001 } 3002 3003 void kvm_arch_accel_class_init(ObjectClass *oc) 3004 { 3005 } 3006 3007 static void kvm_cpu_accel_class_init(ObjectClass *oc, const void *data) 3008 { 3009 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 3010 3011 acc->cpu_target_realize = kvmppc_cpu_realize; 3012 } 3013 3014 static const TypeInfo kvm_cpu_accel_type_info = { 3015 .name = ACCEL_CPU_NAME("kvm"), 3016 3017 .parent = TYPE_ACCEL_CPU, 3018 .class_init = kvm_cpu_accel_class_init, 3019 .abstract = true, 3020 }; 3021 static void kvm_cpu_accel_register_types(void) 3022 { 3023 type_register_static(&kvm_cpu_accel_type_info); 3024 } 3025 type_init(kvm_cpu_accel_register_types); 3026