1ffc672aaSPhilippe Mathieu-Daudé /* 2ffc672aaSPhilippe Mathieu-Daudé * Toshiba TX79-specific instructions translation routines 3ffc672aaSPhilippe Mathieu-Daudé * 4ffc672aaSPhilippe Mathieu-Daudé * Copyright (c) 2018 Fredrik Noring 5ffc672aaSPhilippe Mathieu-Daudé * 6ffc672aaSPhilippe Mathieu-Daudé * SPDX-License-Identifier: GPL-2.0-or-later 7ffc672aaSPhilippe Mathieu-Daudé */ 8ffc672aaSPhilippe Mathieu-Daudé 9ffc672aaSPhilippe Mathieu-Daudé #include "qemu/osdep.h" 10ffc672aaSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 11ffc672aaSPhilippe Mathieu-Daudé #include "exec/helper-gen.h" 12ffc672aaSPhilippe Mathieu-Daudé #include "translate.h" 13ffc672aaSPhilippe Mathieu-Daudé 14ffc672aaSPhilippe Mathieu-Daudé /* Include the auto-generated decoder. */ 15ffc672aaSPhilippe Mathieu-Daudé #include "decode-tx79.c.inc" 16ffc672aaSPhilippe Mathieu-Daudé 17*d27fadddSPhilippe Mathieu-Daudé /* 18*d27fadddSPhilippe Mathieu-Daudé * Overview of the TX79-specific instruction set 19*d27fadddSPhilippe Mathieu-Daudé * ============================================= 20*d27fadddSPhilippe Mathieu-Daudé * 21*d27fadddSPhilippe Mathieu-Daudé * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits 22*d27fadddSPhilippe Mathieu-Daudé * are only used by the specific quadword (128-bit) LQ/SQ load/store 23*d27fadddSPhilippe Mathieu-Daudé * instructions and certain multimedia instructions (MMIs). These MMIs 24*d27fadddSPhilippe Mathieu-Daudé * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit 25*d27fadddSPhilippe Mathieu-Daudé * or sixteen 8-bit paths. 26*d27fadddSPhilippe Mathieu-Daudé * 27*d27fadddSPhilippe Mathieu-Daudé * Reference: 28*d27fadddSPhilippe Mathieu-Daudé * 29*d27fadddSPhilippe Mathieu-Daudé * The Toshiba TX System RISC TX79 Core Architecture manual, 30*d27fadddSPhilippe Mathieu-Daudé * https://wiki.qemu.org/File:C790.pdf 31*d27fadddSPhilippe Mathieu-Daudé */ 32*d27fadddSPhilippe Mathieu-Daudé 33ffc672aaSPhilippe Mathieu-Daudé bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) 34ffc672aaSPhilippe Mathieu-Daudé { 35ffc672aaSPhilippe Mathieu-Daudé if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) { 36ffc672aaSPhilippe Mathieu-Daudé return true; 37ffc672aaSPhilippe Mathieu-Daudé } 38ffc672aaSPhilippe Mathieu-Daudé return false; 39ffc672aaSPhilippe Mathieu-Daudé } 40ffc672aaSPhilippe Mathieu-Daudé 41*d27fadddSPhilippe Mathieu-Daudé /* 42*d27fadddSPhilippe Mathieu-Daudé * Three-Operand Multiply and Multiply-Add (4 instructions) 43*d27fadddSPhilippe Mathieu-Daudé * -------------------------------------------------------- 44*d27fadddSPhilippe Mathieu-Daudé * MADD [rd,] rs, rt Multiply/Add 45*d27fadddSPhilippe Mathieu-Daudé * MADDU [rd,] rs, rt Multiply/Add Unsigned 46*d27fadddSPhilippe Mathieu-Daudé * MULT [rd,] rs, rt Multiply (3-operand) 47*d27fadddSPhilippe Mathieu-Daudé * MULTU [rd,] rs, rt Multiply Unsigned (3-operand) 48*d27fadddSPhilippe Mathieu-Daudé */ 49*d27fadddSPhilippe Mathieu-Daudé 50*d27fadddSPhilippe Mathieu-Daudé /* 51*d27fadddSPhilippe Mathieu-Daudé * Multiply Instructions for Pipeline 1 (10 instructions) 52*d27fadddSPhilippe Mathieu-Daudé * ------------------------------------------------------ 53*d27fadddSPhilippe Mathieu-Daudé * MULT1 [rd,] rs, rt Multiply Pipeline 1 54*d27fadddSPhilippe Mathieu-Daudé * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1 55*d27fadddSPhilippe Mathieu-Daudé * DIV1 rs, rt Divide Pipeline 1 56*d27fadddSPhilippe Mathieu-Daudé * DIVU1 rs, rt Divide Unsigned Pipeline 1 57*d27fadddSPhilippe Mathieu-Daudé * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1 58*d27fadddSPhilippe Mathieu-Daudé * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1 59*d27fadddSPhilippe Mathieu-Daudé * MFHI1 rd Move From HI1 Register 60*d27fadddSPhilippe Mathieu-Daudé * MFLO1 rd Move From LO1 Register 61*d27fadddSPhilippe Mathieu-Daudé * MTHI1 rs Move To HI1 Register 62*d27fadddSPhilippe Mathieu-Daudé * MTLO1 rs Move To LO1 Register 63*d27fadddSPhilippe Mathieu-Daudé */ 64*d27fadddSPhilippe Mathieu-Daudé 65ffc672aaSPhilippe Mathieu-Daudé static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) 66ffc672aaSPhilippe Mathieu-Daudé { 67ffc672aaSPhilippe Mathieu-Daudé gen_store_gpr(cpu_HI[1], a->rd); 68ffc672aaSPhilippe Mathieu-Daudé 69ffc672aaSPhilippe Mathieu-Daudé return true; 70ffc672aaSPhilippe Mathieu-Daudé } 71ffc672aaSPhilippe Mathieu-Daudé 72ffc672aaSPhilippe Mathieu-Daudé static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) 73ffc672aaSPhilippe Mathieu-Daudé { 74ffc672aaSPhilippe Mathieu-Daudé gen_store_gpr(cpu_LO[1], a->rd); 75ffc672aaSPhilippe Mathieu-Daudé 76ffc672aaSPhilippe Mathieu-Daudé return true; 77ffc672aaSPhilippe Mathieu-Daudé } 781f9408d5SPhilippe Mathieu-Daudé 791f9408d5SPhilippe Mathieu-Daudé static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a) 801f9408d5SPhilippe Mathieu-Daudé { 811f9408d5SPhilippe Mathieu-Daudé gen_load_gpr(cpu_HI[1], a->rs); 821f9408d5SPhilippe Mathieu-Daudé 831f9408d5SPhilippe Mathieu-Daudé return true; 841f9408d5SPhilippe Mathieu-Daudé } 851f9408d5SPhilippe Mathieu-Daudé 861f9408d5SPhilippe Mathieu-Daudé static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) 871f9408d5SPhilippe Mathieu-Daudé { 881f9408d5SPhilippe Mathieu-Daudé gen_load_gpr(cpu_LO[1], a->rs); 891f9408d5SPhilippe Mathieu-Daudé 901f9408d5SPhilippe Mathieu-Daudé return true; 911f9408d5SPhilippe Mathieu-Daudé } 925a976c00SPhilippe Mathieu-Daudé 93*d27fadddSPhilippe Mathieu-Daudé /* 94*d27fadddSPhilippe Mathieu-Daudé * Arithmetic (19 instructions) 95*d27fadddSPhilippe Mathieu-Daudé * ---------------------------- 96*d27fadddSPhilippe Mathieu-Daudé * PADDB rd, rs, rt Parallel Add Byte 97*d27fadddSPhilippe Mathieu-Daudé * PSUBB rd, rs, rt Parallel Subtract Byte 98*d27fadddSPhilippe Mathieu-Daudé * PADDH rd, rs, rt Parallel Add Halfword 99*d27fadddSPhilippe Mathieu-Daudé * PSUBH rd, rs, rt Parallel Subtract Halfword 100*d27fadddSPhilippe Mathieu-Daudé * PADDW rd, rs, rt Parallel Add Word 101*d27fadddSPhilippe Mathieu-Daudé * PSUBW rd, rs, rt Parallel Subtract Word 102*d27fadddSPhilippe Mathieu-Daudé * PADSBH rd, rs, rt Parallel Add/Subtract Halfword 103*d27fadddSPhilippe Mathieu-Daudé * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte 104*d27fadddSPhilippe Mathieu-Daudé * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte 105*d27fadddSPhilippe Mathieu-Daudé * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword 106*d27fadddSPhilippe Mathieu-Daudé * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword 107*d27fadddSPhilippe Mathieu-Daudé * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word 108*d27fadddSPhilippe Mathieu-Daudé * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word 109*d27fadddSPhilippe Mathieu-Daudé * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte 110*d27fadddSPhilippe Mathieu-Daudé * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte 111*d27fadddSPhilippe Mathieu-Daudé * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword 112*d27fadddSPhilippe Mathieu-Daudé * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword 113*d27fadddSPhilippe Mathieu-Daudé * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word 114*d27fadddSPhilippe Mathieu-Daudé * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word 115*d27fadddSPhilippe Mathieu-Daudé */ 116*d27fadddSPhilippe Mathieu-Daudé 117*d27fadddSPhilippe Mathieu-Daudé /* 118*d27fadddSPhilippe Mathieu-Daudé * Min/Max (4 instructions) 119*d27fadddSPhilippe Mathieu-Daudé * ------------------------ 120*d27fadddSPhilippe Mathieu-Daudé * PMAXH rd, rs, rt Parallel Maximum Halfword 121*d27fadddSPhilippe Mathieu-Daudé * PMINH rd, rs, rt Parallel Minimum Halfword 122*d27fadddSPhilippe Mathieu-Daudé * PMAXW rd, rs, rt Parallel Maximum Word 123*d27fadddSPhilippe Mathieu-Daudé * PMINW rd, rs, rt Parallel Minimum Word 124*d27fadddSPhilippe Mathieu-Daudé */ 125*d27fadddSPhilippe Mathieu-Daudé 126*d27fadddSPhilippe Mathieu-Daudé /* 127*d27fadddSPhilippe Mathieu-Daudé * Absolute (2 instructions) 128*d27fadddSPhilippe Mathieu-Daudé * ------------------------- 129*d27fadddSPhilippe Mathieu-Daudé * PABSH rd, rt Parallel Absolute Halfword 130*d27fadddSPhilippe Mathieu-Daudé * PABSW rd, rt Parallel Absolute Word 131*d27fadddSPhilippe Mathieu-Daudé */ 132*d27fadddSPhilippe Mathieu-Daudé 133*d27fadddSPhilippe Mathieu-Daudé /* 134*d27fadddSPhilippe Mathieu-Daudé * Logical (4 instructions) 135*d27fadddSPhilippe Mathieu-Daudé * ------------------------ 136*d27fadddSPhilippe Mathieu-Daudé * PAND rd, rs, rt Parallel AND 137*d27fadddSPhilippe Mathieu-Daudé * POR rd, rs, rt Parallel OR 138*d27fadddSPhilippe Mathieu-Daudé * PXOR rd, rs, rt Parallel XOR 139*d27fadddSPhilippe Mathieu-Daudé * PNOR rd, rs, rt Parallel NOR 140*d27fadddSPhilippe Mathieu-Daudé */ 141*d27fadddSPhilippe Mathieu-Daudé 142*d27fadddSPhilippe Mathieu-Daudé /* 143*d27fadddSPhilippe Mathieu-Daudé * Shift (9 instructions) 144*d27fadddSPhilippe Mathieu-Daudé * ---------------------- 145*d27fadddSPhilippe Mathieu-Daudé * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword 146*d27fadddSPhilippe Mathieu-Daudé * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword 147*d27fadddSPhilippe Mathieu-Daudé * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword 148*d27fadddSPhilippe Mathieu-Daudé * PSLLW rd, rt, sa Parallel Shift Left Logical Word 149*d27fadddSPhilippe Mathieu-Daudé * PSRLW rd, rt, sa Parallel Shift Right Logical Word 150*d27fadddSPhilippe Mathieu-Daudé * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word 151*d27fadddSPhilippe Mathieu-Daudé * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word 152*d27fadddSPhilippe Mathieu-Daudé * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word 153*d27fadddSPhilippe Mathieu-Daudé * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word 154*d27fadddSPhilippe Mathieu-Daudé */ 155*d27fadddSPhilippe Mathieu-Daudé 156*d27fadddSPhilippe Mathieu-Daudé /* 157*d27fadddSPhilippe Mathieu-Daudé * Compare (6 instructions) 158*d27fadddSPhilippe Mathieu-Daudé * ------------------------ 159*d27fadddSPhilippe Mathieu-Daudé * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte 160*d27fadddSPhilippe Mathieu-Daudé * PCEQB rd, rs, rt Parallel Compare for Equal Byte 161*d27fadddSPhilippe Mathieu-Daudé * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword 162*d27fadddSPhilippe Mathieu-Daudé * PCEQH rd, rs, rt Parallel Compare for Equal Halfword 163*d27fadddSPhilippe Mathieu-Daudé * PCGTW rd, rs, rt Parallel Compare for Greater Than Word 164*d27fadddSPhilippe Mathieu-Daudé * PCEQW rd, rs, rt Parallel Compare for Equal Word 165*d27fadddSPhilippe Mathieu-Daudé */ 166*d27fadddSPhilippe Mathieu-Daudé 167*d27fadddSPhilippe Mathieu-Daudé /* 168*d27fadddSPhilippe Mathieu-Daudé * LZC (1 instruction) 169*d27fadddSPhilippe Mathieu-Daudé * ------------------- 170*d27fadddSPhilippe Mathieu-Daudé * PLZCW rd, rs Parallel Leading Zero or One Count Word 171*d27fadddSPhilippe Mathieu-Daudé */ 172*d27fadddSPhilippe Mathieu-Daudé 173*d27fadddSPhilippe Mathieu-Daudé /* 174*d27fadddSPhilippe Mathieu-Daudé * Quadword Load and Store (2 instructions) 175*d27fadddSPhilippe Mathieu-Daudé * ---------------------------------------- 176*d27fadddSPhilippe Mathieu-Daudé * LQ rt, offset(base) Load Quadword 177*d27fadddSPhilippe Mathieu-Daudé * SQ rt, offset(base) Store Quadword 178*d27fadddSPhilippe Mathieu-Daudé */ 179*d27fadddSPhilippe Mathieu-Daudé 180*d27fadddSPhilippe Mathieu-Daudé /* 181*d27fadddSPhilippe Mathieu-Daudé * Multiply and Divide (19 instructions) 182*d27fadddSPhilippe Mathieu-Daudé * ------------------------------------- 183*d27fadddSPhilippe Mathieu-Daudé * PMULTW rd, rs, rt Parallel Multiply Word 184*d27fadddSPhilippe Mathieu-Daudé * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word 185*d27fadddSPhilippe Mathieu-Daudé * PDIVW rs, rt Parallel Divide Word 186*d27fadddSPhilippe Mathieu-Daudé * PDIVUW rs, rt Parallel Divide Unsigned Word 187*d27fadddSPhilippe Mathieu-Daudé * PMADDW rd, rs, rt Parallel Multiply-Add Word 188*d27fadddSPhilippe Mathieu-Daudé * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word 189*d27fadddSPhilippe Mathieu-Daudé * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word 190*d27fadddSPhilippe Mathieu-Daudé * PMULTH rd, rs, rt Parallel Multiply Halfword 191*d27fadddSPhilippe Mathieu-Daudé * PMADDH rd, rs, rt Parallel Multiply-Add Halfword 192*d27fadddSPhilippe Mathieu-Daudé * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword 193*d27fadddSPhilippe Mathieu-Daudé * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword 194*d27fadddSPhilippe Mathieu-Daudé * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword 195*d27fadddSPhilippe Mathieu-Daudé * PDIVBW rs, rt Parallel Divide Broadcast Word 196*d27fadddSPhilippe Mathieu-Daudé * PMFHI rd Parallel Move From HI Register 197*d27fadddSPhilippe Mathieu-Daudé * PMFLO rd Parallel Move From LO Register 198*d27fadddSPhilippe Mathieu-Daudé * PMTHI rs Parallel Move To HI Register 199*d27fadddSPhilippe Mathieu-Daudé * PMTLO rs Parallel Move To LO Register 200*d27fadddSPhilippe Mathieu-Daudé * PMFHL rd Parallel Move From HI/LO Register 201*d27fadddSPhilippe Mathieu-Daudé * PMTHL rs Parallel Move To HI/LO Register 202*d27fadddSPhilippe Mathieu-Daudé */ 203*d27fadddSPhilippe Mathieu-Daudé 204*d27fadddSPhilippe Mathieu-Daudé /* 205*d27fadddSPhilippe Mathieu-Daudé * Pack/Extend (11 instructions) 206*d27fadddSPhilippe Mathieu-Daudé * ----------------------------- 207*d27fadddSPhilippe Mathieu-Daudé * PPAC5 rd, rt Parallel Pack to 5 bits 208*d27fadddSPhilippe Mathieu-Daudé * PPACB rd, rs, rt Parallel Pack to Byte 209*d27fadddSPhilippe Mathieu-Daudé * PPACH rd, rs, rt Parallel Pack to Halfword 210*d27fadddSPhilippe Mathieu-Daudé * PPACW rd, rs, rt Parallel Pack to Word 211*d27fadddSPhilippe Mathieu-Daudé * PEXT5 rd, rt Parallel Extend Upper from 5 bits 212*d27fadddSPhilippe Mathieu-Daudé * PEXTUB rd, rs, rt Parallel Extend Upper from Byte 213*d27fadddSPhilippe Mathieu-Daudé * PEXTLB rd, rs, rt Parallel Extend Lower from Byte 214*d27fadddSPhilippe Mathieu-Daudé * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword 215*d27fadddSPhilippe Mathieu-Daudé * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword 216*d27fadddSPhilippe Mathieu-Daudé * PEXTUW rd, rs, rt Parallel Extend Upper from Word 217*d27fadddSPhilippe Mathieu-Daudé * PEXTLW rd, rs, rt Parallel Extend Lower from Word 218*d27fadddSPhilippe Mathieu-Daudé */ 219*d27fadddSPhilippe Mathieu-Daudé 220*d27fadddSPhilippe Mathieu-Daudé /* 221*d27fadddSPhilippe Mathieu-Daudé * Others (16 instructions) 222*d27fadddSPhilippe Mathieu-Daudé * ------------------------ 223*d27fadddSPhilippe Mathieu-Daudé * PCPYH rd, rt Parallel Copy Halfword 224*d27fadddSPhilippe Mathieu-Daudé * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword 225*d27fadddSPhilippe Mathieu-Daudé * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword 226*d27fadddSPhilippe Mathieu-Daudé * PREVH rd, rt Parallel Reverse Halfword 227*d27fadddSPhilippe Mathieu-Daudé * PINTH rd, rs, rt Parallel Interleave Halfword 228*d27fadddSPhilippe Mathieu-Daudé * PINTEH rd, rs, rt Parallel Interleave Even Halfword 229*d27fadddSPhilippe Mathieu-Daudé * PEXEH rd, rt Parallel Exchange Even Halfword 230*d27fadddSPhilippe Mathieu-Daudé * PEXCH rd, rt Parallel Exchange Center Halfword 231*d27fadddSPhilippe Mathieu-Daudé * PEXEW rd, rt Parallel Exchange Even Word 232*d27fadddSPhilippe Mathieu-Daudé * PEXCW rd, rt Parallel Exchange Center Word 233*d27fadddSPhilippe Mathieu-Daudé * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable 234*d27fadddSPhilippe Mathieu-Daudé * MFSA rd Move from Shift Amount Register 235*d27fadddSPhilippe Mathieu-Daudé * MTSA rs Move to Shift Amount Register 236*d27fadddSPhilippe Mathieu-Daudé * MTSAB rs, immediate Move Byte Count to Shift Amount Register 237*d27fadddSPhilippe Mathieu-Daudé * MTSAH rs, immediate Move Halfword Count to Shift Amount Register 238*d27fadddSPhilippe Mathieu-Daudé * PROT3W rd, rt Parallel Rotate 3 Words 239*d27fadddSPhilippe Mathieu-Daudé */ 240*d27fadddSPhilippe Mathieu-Daudé 2415a976c00SPhilippe Mathieu-Daudé /* Parallel Copy Halfword */ 2425a976c00SPhilippe Mathieu-Daudé static bool trans_PCPYH(DisasContext *s, arg_rtype *a) 2435a976c00SPhilippe Mathieu-Daudé { 2445a976c00SPhilippe Mathieu-Daudé if (a->rd == 0) { 2455a976c00SPhilippe Mathieu-Daudé /* nop */ 2465a976c00SPhilippe Mathieu-Daudé return true; 2475a976c00SPhilippe Mathieu-Daudé } 2485a976c00SPhilippe Mathieu-Daudé 2495a976c00SPhilippe Mathieu-Daudé if (a->rt == 0) { 2505a976c00SPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr[a->rd], 0); 2515a976c00SPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 2525a976c00SPhilippe Mathieu-Daudé return true; 2535a976c00SPhilippe Mathieu-Daudé } 2545a976c00SPhilippe Mathieu-Daudé 2555a976c00SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16); 2565a976c00SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32); 2575a976c00SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a->rt], 16, 16); 2585a976c00SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32); 2595a976c00SPhilippe Mathieu-Daudé 2605a976c00SPhilippe Mathieu-Daudé return true; 2615a976c00SPhilippe Mathieu-Daudé } 26294c882f7SPhilippe Mathieu-Daudé 26394c882f7SPhilippe Mathieu-Daudé /* Parallel Copy Lower Doubleword */ 26494c882f7SPhilippe Mathieu-Daudé static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) 26594c882f7SPhilippe Mathieu-Daudé { 26694c882f7SPhilippe Mathieu-Daudé if (a->rd == 0) { 26794c882f7SPhilippe Mathieu-Daudé /* nop */ 26894c882f7SPhilippe Mathieu-Daudé return true; 26994c882f7SPhilippe Mathieu-Daudé } 27094c882f7SPhilippe Mathieu-Daudé 27194c882f7SPhilippe Mathieu-Daudé if (a->rs == 0) { 27294c882f7SPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 27394c882f7SPhilippe Mathieu-Daudé } else { 27494c882f7SPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]); 27594c882f7SPhilippe Mathieu-Daudé } 27694c882f7SPhilippe Mathieu-Daudé 27794c882f7SPhilippe Mathieu-Daudé if (a->rt == 0) { 27894c882f7SPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr[a->rd], 0); 27994c882f7SPhilippe Mathieu-Daudé } else if (a->rd != a->rt) { 28094c882f7SPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]); 28194c882f7SPhilippe Mathieu-Daudé } 28294c882f7SPhilippe Mathieu-Daudé 28394c882f7SPhilippe Mathieu-Daudé return true; 28494c882f7SPhilippe Mathieu-Daudé } 28594c882f7SPhilippe Mathieu-Daudé 28694c882f7SPhilippe Mathieu-Daudé /* Parallel Copy Upper Doubleword */ 28794c882f7SPhilippe Mathieu-Daudé static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) 28894c882f7SPhilippe Mathieu-Daudé { 28994c882f7SPhilippe Mathieu-Daudé if (a->rd == 0) { 29094c882f7SPhilippe Mathieu-Daudé /* nop */ 29194c882f7SPhilippe Mathieu-Daudé return true; 29294c882f7SPhilippe Mathieu-Daudé } 29394c882f7SPhilippe Mathieu-Daudé 29494c882f7SPhilippe Mathieu-Daudé gen_load_gpr_hi(cpu_gpr[a->rd], a->rs); 29594c882f7SPhilippe Mathieu-Daudé 29694c882f7SPhilippe Mathieu-Daudé if (a->rt == 0) { 29794c882f7SPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 29894c882f7SPhilippe Mathieu-Daudé } else if (a->rd != a->rt) { 29994c882f7SPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]); 30094c882f7SPhilippe Mathieu-Daudé } 30194c882f7SPhilippe Mathieu-Daudé 30294c882f7SPhilippe Mathieu-Daudé return true; 30394c882f7SPhilippe Mathieu-Daudé } 304