xref: /qemu/target/mips/tcg/tx79_translate.c (revision 2d4ab117bebb90ad7e7e65629f99f9e82ba32053)
1ffc672aaSPhilippe Mathieu-Daudé /*
2ffc672aaSPhilippe Mathieu-Daudé  * Toshiba TX79-specific instructions translation routines
3ffc672aaSPhilippe Mathieu-Daudé  *
4ffc672aaSPhilippe Mathieu-Daudé  *  Copyright (c) 2018 Fredrik Noring
5*2d4ab117SPhilippe Mathieu-Daudé  *  Copyright (c) 2021 Philippe Mathieu-Daudé
6ffc672aaSPhilippe Mathieu-Daudé  *
7ffc672aaSPhilippe Mathieu-Daudé  * SPDX-License-Identifier: GPL-2.0-or-later
8ffc672aaSPhilippe Mathieu-Daudé  */
9ffc672aaSPhilippe Mathieu-Daudé 
10ffc672aaSPhilippe Mathieu-Daudé #include "qemu/osdep.h"
11ffc672aaSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h"
12ffc672aaSPhilippe Mathieu-Daudé #include "exec/helper-gen.h"
13ffc672aaSPhilippe Mathieu-Daudé #include "translate.h"
14ffc672aaSPhilippe Mathieu-Daudé 
15ffc672aaSPhilippe Mathieu-Daudé /* Include the auto-generated decoder.  */
16ffc672aaSPhilippe Mathieu-Daudé #include "decode-tx79.c.inc"
17ffc672aaSPhilippe Mathieu-Daudé 
18d27fadddSPhilippe Mathieu-Daudé /*
19d27fadddSPhilippe Mathieu-Daudé  *     Overview of the TX79-specific instruction set
20d27fadddSPhilippe Mathieu-Daudé  *     =============================================
21d27fadddSPhilippe Mathieu-Daudé  *
22d27fadddSPhilippe Mathieu-Daudé  * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
23d27fadddSPhilippe Mathieu-Daudé  * are only used by the specific quadword (128-bit) LQ/SQ load/store
24d27fadddSPhilippe Mathieu-Daudé  * instructions and certain multimedia instructions (MMIs). These MMIs
25d27fadddSPhilippe Mathieu-Daudé  * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
26d27fadddSPhilippe Mathieu-Daudé  * or sixteen 8-bit paths.
27d27fadddSPhilippe Mathieu-Daudé  *
28d27fadddSPhilippe Mathieu-Daudé  * Reference:
29d27fadddSPhilippe Mathieu-Daudé  *
30d27fadddSPhilippe Mathieu-Daudé  * The Toshiba TX System RISC TX79 Core Architecture manual,
31d27fadddSPhilippe Mathieu-Daudé  * https://wiki.qemu.org/File:C790.pdf
32d27fadddSPhilippe Mathieu-Daudé  */
33d27fadddSPhilippe Mathieu-Daudé 
34ffc672aaSPhilippe Mathieu-Daudé bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
35ffc672aaSPhilippe Mathieu-Daudé {
36ffc672aaSPhilippe Mathieu-Daudé     if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) {
37ffc672aaSPhilippe Mathieu-Daudé         return true;
38ffc672aaSPhilippe Mathieu-Daudé     }
39ffc672aaSPhilippe Mathieu-Daudé     return false;
40ffc672aaSPhilippe Mathieu-Daudé }
41ffc672aaSPhilippe Mathieu-Daudé 
42d27fadddSPhilippe Mathieu-Daudé /*
43d27fadddSPhilippe Mathieu-Daudé  *     Three-Operand Multiply and Multiply-Add (4 instructions)
44d27fadddSPhilippe Mathieu-Daudé  *     --------------------------------------------------------
45d27fadddSPhilippe Mathieu-Daudé  * MADD    [rd,] rs, rt      Multiply/Add
46d27fadddSPhilippe Mathieu-Daudé  * MADDU   [rd,] rs, rt      Multiply/Add Unsigned
47d27fadddSPhilippe Mathieu-Daudé  * MULT    [rd,] rs, rt      Multiply (3-operand)
48d27fadddSPhilippe Mathieu-Daudé  * MULTU   [rd,] rs, rt      Multiply Unsigned (3-operand)
49d27fadddSPhilippe Mathieu-Daudé  */
50d27fadddSPhilippe Mathieu-Daudé 
51d27fadddSPhilippe Mathieu-Daudé /*
52d27fadddSPhilippe Mathieu-Daudé  *     Multiply Instructions for Pipeline 1 (10 instructions)
53d27fadddSPhilippe Mathieu-Daudé  *     ------------------------------------------------------
54d27fadddSPhilippe Mathieu-Daudé  * MULT1   [rd,] rs, rt      Multiply Pipeline 1
55d27fadddSPhilippe Mathieu-Daudé  * MULTU1  [rd,] rs, rt      Multiply Unsigned Pipeline 1
56d27fadddSPhilippe Mathieu-Daudé  * DIV1    rs, rt            Divide Pipeline 1
57d27fadddSPhilippe Mathieu-Daudé  * DIVU1   rs, rt            Divide Unsigned Pipeline 1
58d27fadddSPhilippe Mathieu-Daudé  * MADD1   [rd,] rs, rt      Multiply-Add Pipeline 1
59d27fadddSPhilippe Mathieu-Daudé  * MADDU1  [rd,] rs, rt      Multiply-Add Unsigned Pipeline 1
60d27fadddSPhilippe Mathieu-Daudé  * MFHI1   rd                Move From HI1 Register
61d27fadddSPhilippe Mathieu-Daudé  * MFLO1   rd                Move From LO1 Register
62d27fadddSPhilippe Mathieu-Daudé  * MTHI1   rs                Move To HI1 Register
63d27fadddSPhilippe Mathieu-Daudé  * MTLO1   rs                Move To LO1 Register
64d27fadddSPhilippe Mathieu-Daudé  */
65d27fadddSPhilippe Mathieu-Daudé 
66ffc672aaSPhilippe Mathieu-Daudé static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a)
67ffc672aaSPhilippe Mathieu-Daudé {
68ffc672aaSPhilippe Mathieu-Daudé     gen_store_gpr(cpu_HI[1], a->rd);
69ffc672aaSPhilippe Mathieu-Daudé 
70ffc672aaSPhilippe Mathieu-Daudé     return true;
71ffc672aaSPhilippe Mathieu-Daudé }
72ffc672aaSPhilippe Mathieu-Daudé 
73ffc672aaSPhilippe Mathieu-Daudé static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a)
74ffc672aaSPhilippe Mathieu-Daudé {
75ffc672aaSPhilippe Mathieu-Daudé     gen_store_gpr(cpu_LO[1], a->rd);
76ffc672aaSPhilippe Mathieu-Daudé 
77ffc672aaSPhilippe Mathieu-Daudé     return true;
78ffc672aaSPhilippe Mathieu-Daudé }
791f9408d5SPhilippe Mathieu-Daudé 
801f9408d5SPhilippe Mathieu-Daudé static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a)
811f9408d5SPhilippe Mathieu-Daudé {
821f9408d5SPhilippe Mathieu-Daudé     gen_load_gpr(cpu_HI[1], a->rs);
831f9408d5SPhilippe Mathieu-Daudé 
841f9408d5SPhilippe Mathieu-Daudé     return true;
851f9408d5SPhilippe Mathieu-Daudé }
861f9408d5SPhilippe Mathieu-Daudé 
871f9408d5SPhilippe Mathieu-Daudé static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
881f9408d5SPhilippe Mathieu-Daudé {
891f9408d5SPhilippe Mathieu-Daudé     gen_load_gpr(cpu_LO[1], a->rs);
901f9408d5SPhilippe Mathieu-Daudé 
911f9408d5SPhilippe Mathieu-Daudé     return true;
921f9408d5SPhilippe Mathieu-Daudé }
935a976c00SPhilippe Mathieu-Daudé 
94d27fadddSPhilippe Mathieu-Daudé /*
95d27fadddSPhilippe Mathieu-Daudé  *     Arithmetic (19 instructions)
96d27fadddSPhilippe Mathieu-Daudé  *     ----------------------------
97d27fadddSPhilippe Mathieu-Daudé  * PADDB   rd, rs, rt        Parallel Add Byte
98d27fadddSPhilippe Mathieu-Daudé  * PSUBB   rd, rs, rt        Parallel Subtract Byte
99d27fadddSPhilippe Mathieu-Daudé  * PADDH   rd, rs, rt        Parallel Add Halfword
100d27fadddSPhilippe Mathieu-Daudé  * PSUBH   rd, rs, rt        Parallel Subtract Halfword
101d27fadddSPhilippe Mathieu-Daudé  * PADDW   rd, rs, rt        Parallel Add Word
102d27fadddSPhilippe Mathieu-Daudé  * PSUBW   rd, rs, rt        Parallel Subtract Word
103d27fadddSPhilippe Mathieu-Daudé  * PADSBH  rd, rs, rt        Parallel Add/Subtract Halfword
104d27fadddSPhilippe Mathieu-Daudé  * PADDSB  rd, rs, rt        Parallel Add with Signed Saturation Byte
105d27fadddSPhilippe Mathieu-Daudé  * PSUBSB  rd, rs, rt        Parallel Subtract with Signed Saturation Byte
106d27fadddSPhilippe Mathieu-Daudé  * PADDSH  rd, rs, rt        Parallel Add with Signed Saturation Halfword
107d27fadddSPhilippe Mathieu-Daudé  * PSUBSH  rd, rs, rt        Parallel Subtract with Signed Saturation Halfword
108d27fadddSPhilippe Mathieu-Daudé  * PADDSW  rd, rs, rt        Parallel Add with Signed Saturation Word
109d27fadddSPhilippe Mathieu-Daudé  * PSUBSW  rd, rs, rt        Parallel Subtract with Signed Saturation Word
110d27fadddSPhilippe Mathieu-Daudé  * PADDUB  rd, rs, rt        Parallel Add with Unsigned saturation Byte
111d27fadddSPhilippe Mathieu-Daudé  * PSUBUB  rd, rs, rt        Parallel Subtract with Unsigned saturation Byte
112d27fadddSPhilippe Mathieu-Daudé  * PADDUH  rd, rs, rt        Parallel Add with Unsigned saturation Halfword
113d27fadddSPhilippe Mathieu-Daudé  * PSUBUH  rd, rs, rt        Parallel Subtract with Unsigned saturation Halfword
114d27fadddSPhilippe Mathieu-Daudé  * PADDUW  rd, rs, rt        Parallel Add with Unsigned saturation Word
115d27fadddSPhilippe Mathieu-Daudé  * PSUBUW  rd, rs, rt        Parallel Subtract with Unsigned saturation Word
116d27fadddSPhilippe Mathieu-Daudé  */
117d27fadddSPhilippe Mathieu-Daudé 
118*2d4ab117SPhilippe Mathieu-Daudé static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a,
119*2d4ab117SPhilippe Mathieu-Daudé                                  void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64))
120*2d4ab117SPhilippe Mathieu-Daudé {
121*2d4ab117SPhilippe Mathieu-Daudé     TCGv_i64 ax, bx;
122*2d4ab117SPhilippe Mathieu-Daudé 
123*2d4ab117SPhilippe Mathieu-Daudé     if (a->rd == 0) {
124*2d4ab117SPhilippe Mathieu-Daudé         /* nop */
125*2d4ab117SPhilippe Mathieu-Daudé         return true;
126*2d4ab117SPhilippe Mathieu-Daudé     }
127*2d4ab117SPhilippe Mathieu-Daudé 
128*2d4ab117SPhilippe Mathieu-Daudé     ax = tcg_temp_new_i64();
129*2d4ab117SPhilippe Mathieu-Daudé     bx = tcg_temp_new_i64();
130*2d4ab117SPhilippe Mathieu-Daudé 
131*2d4ab117SPhilippe Mathieu-Daudé     /* Lower half */
132*2d4ab117SPhilippe Mathieu-Daudé     gen_load_gpr(ax, a->rs);
133*2d4ab117SPhilippe Mathieu-Daudé     gen_load_gpr(bx, a->rt);
134*2d4ab117SPhilippe Mathieu-Daudé     gen_logic_i64(cpu_gpr[a->rd], ax, bx);
135*2d4ab117SPhilippe Mathieu-Daudé 
136*2d4ab117SPhilippe Mathieu-Daudé     /* Upper half */
137*2d4ab117SPhilippe Mathieu-Daudé     gen_load_gpr_hi(ax, a->rs);
138*2d4ab117SPhilippe Mathieu-Daudé     gen_load_gpr_hi(bx, a->rt);
139*2d4ab117SPhilippe Mathieu-Daudé     gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx);
140*2d4ab117SPhilippe Mathieu-Daudé 
141*2d4ab117SPhilippe Mathieu-Daudé     tcg_temp_free(bx);
142*2d4ab117SPhilippe Mathieu-Daudé     tcg_temp_free(ax);
143*2d4ab117SPhilippe Mathieu-Daudé 
144*2d4ab117SPhilippe Mathieu-Daudé     return true;
145*2d4ab117SPhilippe Mathieu-Daudé }
146*2d4ab117SPhilippe Mathieu-Daudé 
147d27fadddSPhilippe Mathieu-Daudé /*
148d27fadddSPhilippe Mathieu-Daudé  *     Min/Max (4 instructions)
149d27fadddSPhilippe Mathieu-Daudé  *     ------------------------
150d27fadddSPhilippe Mathieu-Daudé  * PMAXH   rd, rs, rt        Parallel Maximum Halfword
151d27fadddSPhilippe Mathieu-Daudé  * PMINH   rd, rs, rt        Parallel Minimum Halfword
152d27fadddSPhilippe Mathieu-Daudé  * PMAXW   rd, rs, rt        Parallel Maximum Word
153d27fadddSPhilippe Mathieu-Daudé  * PMINW   rd, rs, rt        Parallel Minimum Word
154d27fadddSPhilippe Mathieu-Daudé  */
155d27fadddSPhilippe Mathieu-Daudé 
156d27fadddSPhilippe Mathieu-Daudé /*
157d27fadddSPhilippe Mathieu-Daudé  *     Absolute (2 instructions)
158d27fadddSPhilippe Mathieu-Daudé  *     -------------------------
159d27fadddSPhilippe Mathieu-Daudé  * PABSH   rd, rt            Parallel Absolute Halfword
160d27fadddSPhilippe Mathieu-Daudé  * PABSW   rd, rt            Parallel Absolute Word
161d27fadddSPhilippe Mathieu-Daudé  */
162d27fadddSPhilippe Mathieu-Daudé 
163d27fadddSPhilippe Mathieu-Daudé /*
164d27fadddSPhilippe Mathieu-Daudé  *     Logical (4 instructions)
165d27fadddSPhilippe Mathieu-Daudé  *     ------------------------
166d27fadddSPhilippe Mathieu-Daudé  * PAND    rd, rs, rt        Parallel AND
167d27fadddSPhilippe Mathieu-Daudé  * POR     rd, rs, rt        Parallel OR
168d27fadddSPhilippe Mathieu-Daudé  * PXOR    rd, rs, rt        Parallel XOR
169d27fadddSPhilippe Mathieu-Daudé  * PNOR    rd, rs, rt        Parallel NOR
170d27fadddSPhilippe Mathieu-Daudé  */
171d27fadddSPhilippe Mathieu-Daudé 
172*2d4ab117SPhilippe Mathieu-Daudé /* Parallel And */
173*2d4ab117SPhilippe Mathieu-Daudé static bool trans_PAND(DisasContext *ctx, arg_rtype *a)
174*2d4ab117SPhilippe Mathieu-Daudé {
175*2d4ab117SPhilippe Mathieu-Daudé     return trans_parallel_arith(ctx, a, tcg_gen_and_i64);
176*2d4ab117SPhilippe Mathieu-Daudé }
177*2d4ab117SPhilippe Mathieu-Daudé 
178*2d4ab117SPhilippe Mathieu-Daudé /* Parallel Or */
179*2d4ab117SPhilippe Mathieu-Daudé static bool trans_POR(DisasContext *ctx, arg_rtype *a)
180*2d4ab117SPhilippe Mathieu-Daudé {
181*2d4ab117SPhilippe Mathieu-Daudé     return trans_parallel_arith(ctx, a, tcg_gen_or_i64);
182*2d4ab117SPhilippe Mathieu-Daudé }
183*2d4ab117SPhilippe Mathieu-Daudé 
184*2d4ab117SPhilippe Mathieu-Daudé /* Parallel Exclusive Or */
185*2d4ab117SPhilippe Mathieu-Daudé static bool trans_PXOR(DisasContext *ctx, arg_rtype *a)
186*2d4ab117SPhilippe Mathieu-Daudé {
187*2d4ab117SPhilippe Mathieu-Daudé     return trans_parallel_arith(ctx, a, tcg_gen_xor_i64);
188*2d4ab117SPhilippe Mathieu-Daudé }
189*2d4ab117SPhilippe Mathieu-Daudé 
190*2d4ab117SPhilippe Mathieu-Daudé /* Parallel Not Or */
191*2d4ab117SPhilippe Mathieu-Daudé static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
192*2d4ab117SPhilippe Mathieu-Daudé {
193*2d4ab117SPhilippe Mathieu-Daudé     return trans_parallel_arith(ctx, a, tcg_gen_nor_i64);
194*2d4ab117SPhilippe Mathieu-Daudé }
195*2d4ab117SPhilippe Mathieu-Daudé 
196d27fadddSPhilippe Mathieu-Daudé /*
197d27fadddSPhilippe Mathieu-Daudé  *     Shift (9 instructions)
198d27fadddSPhilippe Mathieu-Daudé  *     ----------------------
199d27fadddSPhilippe Mathieu-Daudé  * PSLLH   rd, rt, sa        Parallel Shift Left Logical Halfword
200d27fadddSPhilippe Mathieu-Daudé  * PSRLH   rd, rt, sa        Parallel Shift Right Logical Halfword
201d27fadddSPhilippe Mathieu-Daudé  * PSRAH   rd, rt, sa        Parallel Shift Right Arithmetic Halfword
202d27fadddSPhilippe Mathieu-Daudé  * PSLLW   rd, rt, sa        Parallel Shift Left Logical Word
203d27fadddSPhilippe Mathieu-Daudé  * PSRLW   rd, rt, sa        Parallel Shift Right Logical Word
204d27fadddSPhilippe Mathieu-Daudé  * PSRAW   rd, rt, sa        Parallel Shift Right Arithmetic Word
205d27fadddSPhilippe Mathieu-Daudé  * PSLLVW  rd, rt, rs        Parallel Shift Left Logical Variable Word
206d27fadddSPhilippe Mathieu-Daudé  * PSRLVW  rd, rt, rs        Parallel Shift Right Logical Variable Word
207d27fadddSPhilippe Mathieu-Daudé  * PSRAVW  rd, rt, rs        Parallel Shift Right Arithmetic Variable Word
208d27fadddSPhilippe Mathieu-Daudé  */
209d27fadddSPhilippe Mathieu-Daudé 
210d27fadddSPhilippe Mathieu-Daudé /*
211d27fadddSPhilippe Mathieu-Daudé  *     Compare (6 instructions)
212d27fadddSPhilippe Mathieu-Daudé  *     ------------------------
213d27fadddSPhilippe Mathieu-Daudé  * PCGTB   rd, rs, rt        Parallel Compare for Greater Than Byte
214d27fadddSPhilippe Mathieu-Daudé  * PCEQB   rd, rs, rt        Parallel Compare for Equal Byte
215d27fadddSPhilippe Mathieu-Daudé  * PCGTH   rd, rs, rt        Parallel Compare for Greater Than Halfword
216d27fadddSPhilippe Mathieu-Daudé  * PCEQH   rd, rs, rt        Parallel Compare for Equal Halfword
217d27fadddSPhilippe Mathieu-Daudé  * PCGTW   rd, rs, rt        Parallel Compare for Greater Than Word
218d27fadddSPhilippe Mathieu-Daudé  * PCEQW   rd, rs, rt        Parallel Compare for Equal Word
219d27fadddSPhilippe Mathieu-Daudé  */
220d27fadddSPhilippe Mathieu-Daudé 
221d27fadddSPhilippe Mathieu-Daudé /*
222d27fadddSPhilippe Mathieu-Daudé  *     LZC (1 instruction)
223d27fadddSPhilippe Mathieu-Daudé  *     -------------------
224d27fadddSPhilippe Mathieu-Daudé  * PLZCW   rd, rs            Parallel Leading Zero or One Count Word
225d27fadddSPhilippe Mathieu-Daudé  */
226d27fadddSPhilippe Mathieu-Daudé 
227d27fadddSPhilippe Mathieu-Daudé /*
228d27fadddSPhilippe Mathieu-Daudé  *     Quadword Load and Store (2 instructions)
229d27fadddSPhilippe Mathieu-Daudé  *     ----------------------------------------
230d27fadddSPhilippe Mathieu-Daudé  * LQ      rt, offset(base)  Load Quadword
231d27fadddSPhilippe Mathieu-Daudé  * SQ      rt, offset(base)  Store Quadword
232d27fadddSPhilippe Mathieu-Daudé  */
233d27fadddSPhilippe Mathieu-Daudé 
234d27fadddSPhilippe Mathieu-Daudé /*
235d27fadddSPhilippe Mathieu-Daudé  *     Multiply and Divide (19 instructions)
236d27fadddSPhilippe Mathieu-Daudé  *     -------------------------------------
237d27fadddSPhilippe Mathieu-Daudé  * PMULTW  rd, rs, rt        Parallel Multiply Word
238d27fadddSPhilippe Mathieu-Daudé  * PMULTUW rd, rs, rt        Parallel Multiply Unsigned Word
239d27fadddSPhilippe Mathieu-Daudé  * PDIVW   rs, rt            Parallel Divide Word
240d27fadddSPhilippe Mathieu-Daudé  * PDIVUW  rs, rt            Parallel Divide Unsigned Word
241d27fadddSPhilippe Mathieu-Daudé  * PMADDW  rd, rs, rt        Parallel Multiply-Add Word
242d27fadddSPhilippe Mathieu-Daudé  * PMADDUW rd, rs, rt        Parallel Multiply-Add Unsigned Word
243d27fadddSPhilippe Mathieu-Daudé  * PMSUBW  rd, rs, rt        Parallel Multiply-Subtract Word
244d27fadddSPhilippe Mathieu-Daudé  * PMULTH  rd, rs, rt        Parallel Multiply Halfword
245d27fadddSPhilippe Mathieu-Daudé  * PMADDH  rd, rs, rt        Parallel Multiply-Add Halfword
246d27fadddSPhilippe Mathieu-Daudé  * PMSUBH  rd, rs, rt        Parallel Multiply-Subtract Halfword
247d27fadddSPhilippe Mathieu-Daudé  * PHMADH  rd, rs, rt        Parallel Horizontal Multiply-Add Halfword
248d27fadddSPhilippe Mathieu-Daudé  * PHMSBH  rd, rs, rt        Parallel Horizontal Multiply-Subtract Halfword
249d27fadddSPhilippe Mathieu-Daudé  * PDIVBW  rs, rt            Parallel Divide Broadcast Word
250d27fadddSPhilippe Mathieu-Daudé  * PMFHI   rd                Parallel Move From HI Register
251d27fadddSPhilippe Mathieu-Daudé  * PMFLO   rd                Parallel Move From LO Register
252d27fadddSPhilippe Mathieu-Daudé  * PMTHI   rs                Parallel Move To HI Register
253d27fadddSPhilippe Mathieu-Daudé  * PMTLO   rs                Parallel Move To LO Register
254d27fadddSPhilippe Mathieu-Daudé  * PMFHL   rd                Parallel Move From HI/LO Register
255d27fadddSPhilippe Mathieu-Daudé  * PMTHL   rs                Parallel Move To HI/LO Register
256d27fadddSPhilippe Mathieu-Daudé  */
257d27fadddSPhilippe Mathieu-Daudé 
258d27fadddSPhilippe Mathieu-Daudé /*
259d27fadddSPhilippe Mathieu-Daudé  *     Pack/Extend (11 instructions)
260d27fadddSPhilippe Mathieu-Daudé  *     -----------------------------
261d27fadddSPhilippe Mathieu-Daudé  * PPAC5   rd, rt            Parallel Pack to 5 bits
262d27fadddSPhilippe Mathieu-Daudé  * PPACB   rd, rs, rt        Parallel Pack to Byte
263d27fadddSPhilippe Mathieu-Daudé  * PPACH   rd, rs, rt        Parallel Pack to Halfword
264d27fadddSPhilippe Mathieu-Daudé  * PPACW   rd, rs, rt        Parallel Pack to Word
265d27fadddSPhilippe Mathieu-Daudé  * PEXT5   rd, rt            Parallel Extend Upper from 5 bits
266d27fadddSPhilippe Mathieu-Daudé  * PEXTUB  rd, rs, rt        Parallel Extend Upper from Byte
267d27fadddSPhilippe Mathieu-Daudé  * PEXTLB  rd, rs, rt        Parallel Extend Lower from Byte
268d27fadddSPhilippe Mathieu-Daudé  * PEXTUH  rd, rs, rt        Parallel Extend Upper from Halfword
269d27fadddSPhilippe Mathieu-Daudé  * PEXTLH  rd, rs, rt        Parallel Extend Lower from Halfword
270d27fadddSPhilippe Mathieu-Daudé  * PEXTUW  rd, rs, rt        Parallel Extend Upper from Word
271d27fadddSPhilippe Mathieu-Daudé  * PEXTLW  rd, rs, rt        Parallel Extend Lower from Word
272d27fadddSPhilippe Mathieu-Daudé  */
273d27fadddSPhilippe Mathieu-Daudé 
274d27fadddSPhilippe Mathieu-Daudé /*
275d27fadddSPhilippe Mathieu-Daudé  *     Others (16 instructions)
276d27fadddSPhilippe Mathieu-Daudé  *     ------------------------
277d27fadddSPhilippe Mathieu-Daudé  * PCPYH   rd, rt            Parallel Copy Halfword
278d27fadddSPhilippe Mathieu-Daudé  * PCPYLD  rd, rs, rt        Parallel Copy Lower Doubleword
279d27fadddSPhilippe Mathieu-Daudé  * PCPYUD  rd, rs, rt        Parallel Copy Upper Doubleword
280d27fadddSPhilippe Mathieu-Daudé  * PREVH   rd, rt            Parallel Reverse Halfword
281d27fadddSPhilippe Mathieu-Daudé  * PINTH   rd, rs, rt        Parallel Interleave Halfword
282d27fadddSPhilippe Mathieu-Daudé  * PINTEH  rd, rs, rt        Parallel Interleave Even Halfword
283d27fadddSPhilippe Mathieu-Daudé  * PEXEH   rd, rt            Parallel Exchange Even Halfword
284d27fadddSPhilippe Mathieu-Daudé  * PEXCH   rd, rt            Parallel Exchange Center Halfword
285d27fadddSPhilippe Mathieu-Daudé  * PEXEW   rd, rt            Parallel Exchange Even Word
286d27fadddSPhilippe Mathieu-Daudé  * PEXCW   rd, rt            Parallel Exchange Center Word
287d27fadddSPhilippe Mathieu-Daudé  * QFSRV   rd, rs, rt        Quadword Funnel Shift Right Variable
288d27fadddSPhilippe Mathieu-Daudé  * MFSA    rd                Move from Shift Amount Register
289d27fadddSPhilippe Mathieu-Daudé  * MTSA    rs                Move to Shift Amount Register
290d27fadddSPhilippe Mathieu-Daudé  * MTSAB   rs, immediate     Move Byte Count to Shift Amount Register
291d27fadddSPhilippe Mathieu-Daudé  * MTSAH   rs, immediate     Move Halfword Count to Shift Amount Register
292d27fadddSPhilippe Mathieu-Daudé  * PROT3W  rd, rt            Parallel Rotate 3 Words
293d27fadddSPhilippe Mathieu-Daudé  */
294d27fadddSPhilippe Mathieu-Daudé 
2955a976c00SPhilippe Mathieu-Daudé /* Parallel Copy Halfword */
2965a976c00SPhilippe Mathieu-Daudé static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
2975a976c00SPhilippe Mathieu-Daudé {
2985a976c00SPhilippe Mathieu-Daudé     if (a->rd == 0) {
2995a976c00SPhilippe Mathieu-Daudé         /* nop */
3005a976c00SPhilippe Mathieu-Daudé         return true;
3015a976c00SPhilippe Mathieu-Daudé     }
3025a976c00SPhilippe Mathieu-Daudé 
3035a976c00SPhilippe Mathieu-Daudé     if (a->rt == 0) {
3045a976c00SPhilippe Mathieu-Daudé         tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
3055a976c00SPhilippe Mathieu-Daudé         tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
3065a976c00SPhilippe Mathieu-Daudé         return true;
3075a976c00SPhilippe Mathieu-Daudé     }
3085a976c00SPhilippe Mathieu-Daudé 
3095a976c00SPhilippe Mathieu-Daudé     tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16);
3105a976c00SPhilippe Mathieu-Daudé     tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32);
3115a976c00SPhilippe Mathieu-Daudé     tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a->rt], 16, 16);
3125a976c00SPhilippe Mathieu-Daudé     tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32);
3135a976c00SPhilippe Mathieu-Daudé 
3145a976c00SPhilippe Mathieu-Daudé     return true;
3155a976c00SPhilippe Mathieu-Daudé }
31694c882f7SPhilippe Mathieu-Daudé 
31794c882f7SPhilippe Mathieu-Daudé /* Parallel Copy Lower Doubleword */
31894c882f7SPhilippe Mathieu-Daudé static bool trans_PCPYLD(DisasContext *s, arg_rtype *a)
31994c882f7SPhilippe Mathieu-Daudé {
32094c882f7SPhilippe Mathieu-Daudé     if (a->rd == 0) {
32194c882f7SPhilippe Mathieu-Daudé         /* nop */
32294c882f7SPhilippe Mathieu-Daudé         return true;
32394c882f7SPhilippe Mathieu-Daudé     }
32494c882f7SPhilippe Mathieu-Daudé 
32594c882f7SPhilippe Mathieu-Daudé     if (a->rs == 0) {
32694c882f7SPhilippe Mathieu-Daudé         tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
32794c882f7SPhilippe Mathieu-Daudé     } else {
32894c882f7SPhilippe Mathieu-Daudé         tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]);
32994c882f7SPhilippe Mathieu-Daudé     }
33094c882f7SPhilippe Mathieu-Daudé 
33194c882f7SPhilippe Mathieu-Daudé     if (a->rt == 0) {
33294c882f7SPhilippe Mathieu-Daudé         tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
33394c882f7SPhilippe Mathieu-Daudé     } else if (a->rd != a->rt) {
33494c882f7SPhilippe Mathieu-Daudé         tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]);
33594c882f7SPhilippe Mathieu-Daudé     }
33694c882f7SPhilippe Mathieu-Daudé 
33794c882f7SPhilippe Mathieu-Daudé     return true;
33894c882f7SPhilippe Mathieu-Daudé }
33994c882f7SPhilippe Mathieu-Daudé 
34094c882f7SPhilippe Mathieu-Daudé /* Parallel Copy Upper Doubleword */
34194c882f7SPhilippe Mathieu-Daudé static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
34294c882f7SPhilippe Mathieu-Daudé {
34394c882f7SPhilippe Mathieu-Daudé     if (a->rd == 0) {
34494c882f7SPhilippe Mathieu-Daudé         /* nop */
34594c882f7SPhilippe Mathieu-Daudé         return true;
34694c882f7SPhilippe Mathieu-Daudé     }
34794c882f7SPhilippe Mathieu-Daudé 
34894c882f7SPhilippe Mathieu-Daudé     gen_load_gpr_hi(cpu_gpr[a->rd], a->rs);
34994c882f7SPhilippe Mathieu-Daudé 
35094c882f7SPhilippe Mathieu-Daudé     if (a->rt == 0) {
35194c882f7SPhilippe Mathieu-Daudé         tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
35294c882f7SPhilippe Mathieu-Daudé     } else if (a->rd != a->rt) {
35394c882f7SPhilippe Mathieu-Daudé         tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]);
35494c882f7SPhilippe Mathieu-Daudé     }
35594c882f7SPhilippe Mathieu-Daudé 
35694c882f7SPhilippe Mathieu-Daudé     return true;
35794c882f7SPhilippe Mathieu-Daudé }
358