1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "system/qtest.h" 14 #include "system/tcg.h" 15 #include "system/kvm.h" 16 #include "kvm/kvm_loongarch.h" 17 #include "hw/qdev-properties.h" 18 #include "exec/translation-block.h" 19 #include "cpu.h" 20 #include "internals.h" 21 #include "fpu/softfloat-helpers.h" 22 #include "csr.h" 23 #ifndef CONFIG_USER_ONLY 24 #include "system/reset.h" 25 #endif 26 #include "vec.h" 27 #ifdef CONFIG_KVM 28 #include <linux/kvm.h> 29 #endif 30 #ifdef CONFIG_TCG 31 #include "accel/tcg/cpu-ldst.h" 32 #include "accel/tcg/cpu-ops.h" 33 #include "tcg/tcg.h" 34 #endif 35 #include "tcg/tcg_loongarch.h" 36 37 const char * const regnames[32] = { 38 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 39 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 40 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 41 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 42 }; 43 44 const char * const fregnames[32] = { 45 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 46 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 47 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 48 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 49 }; 50 51 struct TypeExcp { 52 int32_t exccode; 53 const char * const name; 54 }; 55 56 static const struct TypeExcp excp_names[] = { 57 {EXCCODE_INT, "Interrupt"}, 58 {EXCCODE_PIL, "Page invalid exception for load"}, 59 {EXCCODE_PIS, "Page invalid exception for store"}, 60 {EXCCODE_PIF, "Page invalid exception for fetch"}, 61 {EXCCODE_PME, "Page modified exception"}, 62 {EXCCODE_PNR, "Page Not Readable exception"}, 63 {EXCCODE_PNX, "Page Not Executable exception"}, 64 {EXCCODE_PPI, "Page Privilege error"}, 65 {EXCCODE_ADEF, "Address error for instruction fetch"}, 66 {EXCCODE_ADEM, "Address error for Memory access"}, 67 {EXCCODE_SYS, "Syscall"}, 68 {EXCCODE_BRK, "Break"}, 69 {EXCCODE_INE, "Instruction Non-Existent"}, 70 {EXCCODE_IPE, "Instruction privilege error"}, 71 {EXCCODE_FPD, "Floating Point Disabled"}, 72 {EXCCODE_FPE, "Floating Point Exception"}, 73 {EXCCODE_DBP, "Debug breakpoint"}, 74 {EXCCODE_BCE, "Bound Check Exception"}, 75 {EXCCODE_SXD, "128 bit vector instructions Disable exception"}, 76 {EXCCODE_ASXD, "256 bit vector instructions Disable exception"}, 77 {EXCP_HLT, "EXCP_HLT"}, 78 }; 79 80 const char *loongarch_exception_name(int32_t exception) 81 { 82 int i; 83 84 for (i = 0; i < ARRAY_SIZE(excp_names); i++) { 85 if (excp_names[i].exccode == exception) { 86 return excp_names[i].name; 87 } 88 } 89 return "Unknown"; 90 } 91 92 void G_NORETURN do_raise_exception(CPULoongArchState *env, 93 uint32_t exception, 94 uintptr_t pc) 95 { 96 CPUState *cs = env_cpu(env); 97 98 qemu_log_mask(CPU_LOG_INT, "%s: exception: %d (%s)\n", 99 __func__, 100 exception, 101 loongarch_exception_name(exception)); 102 cs->exception_index = exception; 103 104 cpu_loop_exit_restore(cs, pc); 105 } 106 107 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 108 { 109 set_pc(cpu_env(cs), value); 110 } 111 112 static vaddr loongarch_cpu_get_pc(CPUState *cs) 113 { 114 return cpu_env(cs)->pc; 115 } 116 117 #ifndef CONFIG_USER_ONLY 118 #include "hw/loongarch/virt.h" 119 120 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 121 { 122 LoongArchCPU *cpu = opaque; 123 CPULoongArchState *env = &cpu->env; 124 CPUState *cs = CPU(cpu); 125 126 if (irq < 0 || irq >= N_IRQS) { 127 return; 128 } 129 130 if (kvm_enabled()) { 131 kvm_loongarch_set_interrupt(cpu, irq, level); 132 } else if (tcg_enabled()) { 133 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 134 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 135 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 136 } else { 137 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 138 } 139 } 140 } 141 142 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 143 { 144 bool ret = 0; 145 146 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 147 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 148 149 return ret; 150 } 151 152 /* Check if there is pending and not masked out interrupt */ 153 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 154 { 155 uint32_t pending; 156 uint32_t status; 157 158 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 159 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 160 161 return (pending & status) != 0; 162 } 163 #endif 164 165 #ifdef CONFIG_TCG 166 #ifndef CONFIG_USER_ONLY 167 static void loongarch_cpu_do_interrupt(CPUState *cs) 168 { 169 CPULoongArchState *env = cpu_env(cs); 170 bool update_badinstr = 1; 171 int cause = -1; 172 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 173 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 174 175 if (cs->exception_index != EXCCODE_INT) { 176 qemu_log_mask(CPU_LOG_INT, 177 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 178 " TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n", 179 __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA, 180 cs->exception_index, 181 loongarch_exception_name(cs->exception_index)); 182 } 183 184 switch (cs->exception_index) { 185 case EXCCODE_DBP: 186 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 187 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 188 goto set_DERA; 189 set_DERA: 190 env->CSR_DERA = env->pc; 191 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 192 set_pc(env, env->CSR_EENTRY + 0x480); 193 break; 194 case EXCCODE_INT: 195 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 196 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 197 goto set_DERA; 198 } 199 QEMU_FALLTHROUGH; 200 case EXCCODE_PIF: 201 case EXCCODE_ADEF: 202 cause = cs->exception_index; 203 update_badinstr = 0; 204 break; 205 case EXCCODE_SYS: 206 case EXCCODE_BRK: 207 case EXCCODE_INE: 208 case EXCCODE_IPE: 209 case EXCCODE_FPD: 210 case EXCCODE_FPE: 211 case EXCCODE_SXD: 212 case EXCCODE_ASXD: 213 env->CSR_BADV = env->pc; 214 QEMU_FALLTHROUGH; 215 case EXCCODE_BCE: 216 case EXCCODE_ADEM: 217 case EXCCODE_PIL: 218 case EXCCODE_PIS: 219 case EXCCODE_PME: 220 case EXCCODE_PNR: 221 case EXCCODE_PNX: 222 case EXCCODE_PPI: 223 cause = cs->exception_index; 224 break; 225 default: 226 qemu_log("Error: exception(%d) has not been supported\n", 227 cs->exception_index); 228 abort(); 229 } 230 231 if (update_badinstr) { 232 env->CSR_BADI = cpu_ldl_code(env, env->pc); 233 } 234 235 /* Save PLV and IE */ 236 if (tlbfill) { 237 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 238 FIELD_EX64(env->CSR_CRMD, 239 CSR_CRMD, PLV)); 240 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 241 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 242 /* set the DA mode */ 243 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 244 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 245 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 246 PC, (env->pc >> 2)); 247 } else { 248 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, 249 EXCODE_MCODE(cause)); 250 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, 251 EXCODE_SUBCODE(cause)); 252 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 253 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 254 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 255 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 256 env->CSR_ERA = env->pc; 257 } 258 259 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 260 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 261 262 if (vec_size) { 263 vec_size = (1 << vec_size) * 4; 264 } 265 266 if (cs->exception_index == EXCCODE_INT) { 267 /* Interrupt */ 268 uint32_t vector = 0; 269 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 270 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 271 272 /* Find the highest-priority interrupt. */ 273 vector = 31 - clz32(pending); 274 set_pc(env, env->CSR_EENTRY + \ 275 (EXCCODE_EXTERNAL_INT + vector) * vec_size); 276 qemu_log_mask(CPU_LOG_INT, 277 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 278 " cause %d\n" " A " TARGET_FMT_lx " D " 279 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 280 TARGET_FMT_lx "\n", 281 __func__, env->pc, env->CSR_ERA, 282 cause, env->CSR_BADV, env->CSR_DERA, vector, 283 env->CSR_ECFG, env->CSR_ESTAT); 284 } else { 285 if (tlbfill) { 286 set_pc(env, env->CSR_TLBRENTRY); 287 } else { 288 set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); 289 } 290 qemu_log_mask(CPU_LOG_INT, 291 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 292 " cause %d%s\n, ESTAT " TARGET_FMT_lx 293 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 294 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 295 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 296 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 297 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 298 env->CSR_ECFG, 299 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 300 env->CSR_BADI, env->gpr[11], cs->cpu_index, 301 env->CSR_ASID); 302 } 303 cs->exception_index = -1; 304 } 305 306 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 307 vaddr addr, unsigned size, 308 MMUAccessType access_type, 309 int mmu_idx, MemTxAttrs attrs, 310 MemTxResult response, 311 uintptr_t retaddr) 312 { 313 CPULoongArchState *env = cpu_env(cs); 314 315 if (access_type == MMU_INST_FETCH) { 316 do_raise_exception(env, EXCCODE_ADEF, retaddr); 317 } else { 318 do_raise_exception(env, EXCCODE_ADEM, retaddr); 319 } 320 } 321 322 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 323 { 324 if (interrupt_request & CPU_INTERRUPT_HARD) { 325 CPULoongArchState *env = cpu_env(cs); 326 327 if (cpu_loongarch_hw_interrupts_enabled(env) && 328 cpu_loongarch_hw_interrupts_pending(env)) { 329 /* Raise it */ 330 cs->exception_index = EXCCODE_INT; 331 loongarch_cpu_do_interrupt(cs); 332 return true; 333 } 334 } 335 return false; 336 } 337 #endif 338 339 void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, 340 uint64_t *cs_base, uint32_t *flags) 341 { 342 *pc = env->pc; 343 *cs_base = 0; 344 *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); 345 *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; 346 *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; 347 *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; 348 *flags |= is_va32(env) * HW_FLAGS_VA32; 349 } 350 351 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 352 const TranslationBlock *tb) 353 { 354 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 355 set_pc(cpu_env(cs), tb->pc); 356 } 357 358 static void loongarch_restore_state_to_opc(CPUState *cs, 359 const TranslationBlock *tb, 360 const uint64_t *data) 361 { 362 set_pc(cpu_env(cs), data[0]); 363 } 364 #endif /* CONFIG_TCG */ 365 366 #ifndef CONFIG_USER_ONLY 367 static bool loongarch_cpu_has_work(CPUState *cs) 368 { 369 bool has_work = false; 370 371 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 372 cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) { 373 has_work = true; 374 } 375 376 return has_work; 377 } 378 #endif /* !CONFIG_USER_ONLY */ 379 380 static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) 381 { 382 CPULoongArchState *env = cpu_env(cs); 383 384 if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { 385 return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); 386 } 387 return MMU_DA_IDX; 388 } 389 390 static void loongarch_la464_init_csr(Object *obj) 391 { 392 #ifndef CONFIG_USER_ONLY 393 static bool initialized; 394 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 395 CPULoongArchState *env = &cpu->env; 396 int i, num; 397 398 if (!initialized) { 399 initialized = true; 400 num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM); 401 for (i = num; i < 16; i++) { 402 set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED); 403 } 404 set_csr_flag(LOONGARCH_CSR_IMPCTL1, CSRFL_UNUSED); 405 set_csr_flag(LOONGARCH_CSR_IMPCTL2, CSRFL_UNUSED); 406 set_csr_flag(LOONGARCH_CSR_MERRCTL, CSRFL_UNUSED); 407 set_csr_flag(LOONGARCH_CSR_MERRINFO1, CSRFL_UNUSED); 408 set_csr_flag(LOONGARCH_CSR_MERRINFO2, CSRFL_UNUSED); 409 set_csr_flag(LOONGARCH_CSR_MERRENTRY, CSRFL_UNUSED); 410 set_csr_flag(LOONGARCH_CSR_MERRERA, CSRFL_UNUSED); 411 set_csr_flag(LOONGARCH_CSR_MERRSAVE, CSRFL_UNUSED); 412 set_csr_flag(LOONGARCH_CSR_CTAG, CSRFL_UNUSED); 413 } 414 #endif 415 } 416 417 static void loongarch_la464_initfn(Object *obj) 418 { 419 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 420 CPULoongArchState *env = &cpu->env; 421 uint32_t data = 0, field; 422 int i; 423 424 for (i = 0; i < 21; i++) { 425 env->cpucfg[i] = 0x0; 426 } 427 428 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; 429 env->cpucfg[0] = 0x14c010; /* PRID */ 430 431 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 432 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 433 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 434 if (kvm_enabled()) { 435 /* GPA address width of VM is 47, field value is 47 - 1 */ 436 field = 0x2e; 437 } else { 438 field = 0x2f; /* 48 bit - 1 */ 439 } 440 data = FIELD_DP32(data, CPUCFG1, PALEN, field); 441 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 442 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 443 data = FIELD_DP32(data, CPUCFG1, RI, 1); 444 data = FIELD_DP32(data, CPUCFG1, EP, 1); 445 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 446 data = FIELD_DP32(data, CPUCFG1, HP, 1); 447 data = FIELD_DP32(data, CPUCFG1, CRC, 1); 448 env->cpucfg[1] = data; 449 450 data = 0; 451 data = FIELD_DP32(data, CPUCFG2, FP, 1); 452 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 453 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 454 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 455 data = FIELD_DP32(data, CPUCFG2, LSX, 1), 456 data = FIELD_DP32(data, CPUCFG2, LASX, 1), 457 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 458 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 459 data = FIELD_DP32(data, CPUCFG2, LSPW, 1); 460 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 461 env->cpucfg[2] = data; 462 463 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 464 465 data = 0; 466 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 467 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 468 env->cpucfg[5] = data; 469 470 data = 0; 471 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 472 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 473 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 474 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 475 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 476 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 477 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 478 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 479 env->cpucfg[16] = data; 480 481 data = 0; 482 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 483 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 484 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 485 env->cpucfg[17] = data; 486 487 data = 0; 488 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 489 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 490 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 491 env->cpucfg[18] = data; 492 493 data = 0; 494 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 495 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 496 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 497 env->cpucfg[19] = data; 498 499 data = 0; 500 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 501 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 502 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); 503 env->cpucfg[20] = data; 504 505 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 506 507 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, 8); 508 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS, 0x2f); 509 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 7); 510 511 env->CSR_PRCFG2 = 0x3ffff000; 512 513 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 514 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 515 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 516 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 517 518 loongarch_la464_init_csr(obj); 519 loongarch_cpu_post_init(obj); 520 } 521 522 static void loongarch_la132_initfn(Object *obj) 523 { 524 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 525 CPULoongArchState *env = &cpu->env; 526 uint32_t data = 0; 527 int i; 528 529 for (i = 0; i < 21; i++) { 530 env->cpucfg[i] = 0x0; 531 } 532 533 cpu->dtb_compatible = "loongarch,Loongson-1C103"; 534 env->cpucfg[0] = 0x148042; /* PRID */ 535 536 data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ 537 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 538 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 539 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ 540 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ 541 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 542 data = FIELD_DP32(data, CPUCFG1, RI, 0); 543 data = FIELD_DP32(data, CPUCFG1, EP, 0); 544 data = FIELD_DP32(data, CPUCFG1, RPLV, 0); 545 data = FIELD_DP32(data, CPUCFG1, HP, 1); 546 data = FIELD_DP32(data, CPUCFG1, CRC, 1); 547 env->cpucfg[1] = data; 548 } 549 550 static void loongarch_max_initfn(Object *obj) 551 { 552 /* '-cpu max' for TCG: we use cpu la464. */ 553 loongarch_la464_initfn(obj); 554 } 555 556 static void loongarch_cpu_reset_hold(Object *obj, ResetType type) 557 { 558 uint8_t tlb_ps; 559 CPUState *cs = CPU(obj); 560 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(obj); 561 CPULoongArchState *env = cpu_env(cs); 562 563 if (lacc->parent_phases.hold) { 564 lacc->parent_phases.hold(obj, type); 565 } 566 567 #ifdef CONFIG_TCG 568 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 569 #endif 570 env->fcsr0 = 0x0; 571 572 int n; 573 /* Set csr registers value after reset, see the manual 6.4. */ 574 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 575 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 576 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 577 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 578 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 0); 579 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 0); 580 581 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 582 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 583 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 584 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 585 586 env->CSR_MISC = 0; 587 588 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 589 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 590 591 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 592 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 593 env->CSR_CPUID = cs->cpu_index; 594 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 595 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 596 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 597 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 598 env->CSR_TID = cs->cpu_index; 599 /* 600 * Workaround for edk2-stable202408, CSR PGD register is set only if 601 * its value is equal to zero for boot cpu, it causes reboot issue. 602 * 603 * Here clear CSR registers relative with TLB. 604 */ 605 env->CSR_PGDH = 0; 606 env->CSR_PGDL = 0; 607 env->CSR_PWCH = 0; 608 env->CSR_EENTRY = 0; 609 env->CSR_TLBRENTRY = 0; 610 env->CSR_MERRENTRY = 0; 611 /* set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits from CSR_PRCFG2 */ 612 if (env->CSR_PRCFG2 == 0) { 613 env->CSR_PRCFG2 = 0x3fffff000; 614 } 615 tlb_ps = ctz32(env->CSR_PRCFG2); 616 env->CSR_STLBPS = FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS, tlb_ps); 617 env->CSR_PWCL = FIELD_DP64(env->CSR_PWCL, CSR_PWCL, PTBASE, tlb_ps); 618 for (n = 0; n < 4; n++) { 619 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 620 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 621 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 622 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 623 } 624 625 #ifndef CONFIG_USER_ONLY 626 env->pc = 0x1c000000; 627 #ifdef CONFIG_TCG 628 memset(env->tlb, 0, sizeof(env->tlb)); 629 #endif 630 if (kvm_enabled()) { 631 kvm_arch_reset_vcpu(cs); 632 } 633 #endif 634 635 #ifdef CONFIG_TCG 636 restore_fp_status(env); 637 #endif 638 cs->exception_index = -1; 639 } 640 641 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 642 { 643 info->endian = BFD_ENDIAN_LITTLE; 644 info->print_insn = print_insn_loongarch; 645 } 646 647 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 648 { 649 CPUState *cs = CPU(dev); 650 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 651 Error *local_err = NULL; 652 653 cpu_exec_realizefn(cs, &local_err); 654 if (local_err != NULL) { 655 error_propagate(errp, local_err); 656 return; 657 } 658 659 loongarch_cpu_register_gdb_regs_for_features(cs); 660 661 qemu_init_vcpu(cs); 662 cpu_reset(cs); 663 664 lacc->parent_realize(dev, errp); 665 } 666 667 static void loongarch_cpu_unrealizefn(DeviceState *dev) 668 { 669 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 670 671 #ifndef CONFIG_USER_ONLY 672 cpu_remove_sync(CPU(dev)); 673 #endif 674 675 lacc->parent_unrealize(dev); 676 } 677 678 static bool loongarch_get_lsx(Object *obj, Error **errp) 679 { 680 return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF; 681 } 682 683 static void loongarch_set_lsx(Object *obj, bool value, Error **errp) 684 { 685 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 686 uint32_t val; 687 688 cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 689 if (cpu->lsx == ON_OFF_AUTO_OFF) { 690 cpu->lasx = ON_OFF_AUTO_OFF; 691 if (cpu->lasx == ON_OFF_AUTO_ON) { 692 error_setg(errp, "Failed to disable LSX since LASX is enabled"); 693 return; 694 } 695 } 696 697 if (kvm_enabled()) { 698 /* kvm feature detection in function kvm_arch_init_vcpu */ 699 return; 700 } 701 702 /* LSX feature detection in TCG mode */ 703 val = cpu->env.cpucfg[2]; 704 if (cpu->lsx == ON_OFF_AUTO_ON) { 705 if (FIELD_EX32(val, CPUCFG2, LSX) == 0) { 706 error_setg(errp, "Failed to enable LSX in TCG mode"); 707 return; 708 } 709 } else { 710 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0); 711 val = cpu->env.cpucfg[2]; 712 } 713 714 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value); 715 } 716 717 static bool loongarch_get_lasx(Object *obj, Error **errp) 718 { 719 return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF; 720 } 721 722 static void loongarch_set_lasx(Object *obj, bool value, Error **errp) 723 { 724 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 725 uint32_t val; 726 727 cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 728 if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) { 729 error_setg(errp, "Failed to enable LASX since lSX is disabled"); 730 return; 731 } 732 733 if (kvm_enabled()) { 734 /* kvm feature detection in function kvm_arch_init_vcpu */ 735 return; 736 } 737 738 /* LASX feature detection in TCG mode */ 739 val = cpu->env.cpucfg[2]; 740 if (cpu->lasx == ON_OFF_AUTO_ON) { 741 if (FIELD_EX32(val, CPUCFG2, LASX) == 0) { 742 error_setg(errp, "Failed to enable LASX in TCG mode"); 743 return; 744 } 745 } 746 747 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value); 748 } 749 750 void loongarch_cpu_post_init(Object *obj) 751 { 752 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 753 754 cpu->lbt = ON_OFF_AUTO_OFF; 755 cpu->pmu = ON_OFF_AUTO_OFF; 756 cpu->lsx = ON_OFF_AUTO_AUTO; 757 cpu->lasx = ON_OFF_AUTO_AUTO; 758 object_property_add_bool(obj, "lsx", loongarch_get_lsx, 759 loongarch_set_lsx); 760 object_property_add_bool(obj, "lasx", loongarch_get_lasx, 761 loongarch_set_lasx); 762 /* lbt is enabled only in kvm mode, not supported in tcg mode */ 763 if (kvm_enabled()) { 764 kvm_loongarch_cpu_post_init(cpu); 765 } 766 } 767 768 static void loongarch_cpu_init(Object *obj) 769 { 770 #ifndef CONFIG_USER_ONLY 771 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 772 773 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 774 #ifdef CONFIG_TCG 775 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 776 &loongarch_constant_timer_cb, cpu); 777 #endif 778 #endif 779 } 780 781 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 782 { 783 ObjectClass *oc; 784 785 oc = object_class_by_name(cpu_model); 786 if (!oc) { 787 g_autofree char *typename 788 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 789 oc = object_class_by_name(typename); 790 } 791 792 return oc; 793 } 794 795 static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f) 796 { 797 #ifndef CONFIG_USER_ONLY 798 CPULoongArchState *env = cpu_env(cs); 799 CSRInfo *csr_info; 800 int64_t *addr; 801 int i, j, len, col = 0; 802 803 qemu_fprintf(f, "\n"); 804 805 /* Dump all generic CSR register */ 806 for (i = 0; i < LOONGARCH_CSR_DBG; i++) { 807 csr_info = get_csr(i); 808 if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) { 809 if (i == (col + 3)) { 810 qemu_fprintf(f, "\n"); 811 } 812 813 continue; 814 } 815 816 if ((i > (col + 3)) || (i == col)) { 817 col = i & ~3; 818 qemu_fprintf(f, " CSR%03d:", col); 819 } 820 821 addr = (void *)env + csr_info->offset; 822 qemu_fprintf(f, " %s ", csr_info->name); 823 len = strlen(csr_info->name); 824 for (; len < 6; len++) { 825 qemu_fprintf(f, " "); 826 } 827 828 qemu_fprintf(f, "%" PRIx64, *addr); 829 j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1); 830 len += j / 4 + 1; 831 for (; len < 22; len++) { 832 qemu_fprintf(f, " "); 833 } 834 835 if (i == (col + 3)) { 836 qemu_fprintf(f, "\n"); 837 } 838 } 839 qemu_fprintf(f, "\n"); 840 #endif 841 } 842 843 static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 844 { 845 CPULoongArchState *env = cpu_env(cs); 846 int i; 847 848 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 849 qemu_fprintf(f, " FCSR0 0x%08x\n", env->fcsr0); 850 851 /* gpr */ 852 for (i = 0; i < 32; i++) { 853 if ((i & 3) == 0) { 854 qemu_fprintf(f, " GPR%02d:", i); 855 } 856 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 857 if ((i & 3) == 3) { 858 qemu_fprintf(f, "\n"); 859 } 860 } 861 862 /* csr */ 863 loongarch_cpu_dump_csr(cs, f); 864 865 /* fpr */ 866 if (flags & CPU_DUMP_FPU) { 867 for (i = 0; i < 32; i++) { 868 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i].vreg.D(0)); 869 if ((i & 3) == 3) { 870 qemu_fprintf(f, "\n"); 871 } 872 } 873 } 874 } 875 876 #ifdef CONFIG_TCG 877 static const TCGCPUOps loongarch_tcg_ops = { 878 .guest_default_memory_order = 0, 879 .mttcg_supported = true, 880 881 .initialize = loongarch_translate_init, 882 .translate_code = loongarch_translate_code, 883 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 884 .restore_state_to_opc = loongarch_restore_state_to_opc, 885 .mmu_index = loongarch_cpu_mmu_index, 886 887 #ifndef CONFIG_USER_ONLY 888 .tlb_fill = loongarch_cpu_tlb_fill, 889 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 890 .cpu_exec_halt = loongarch_cpu_has_work, 891 .cpu_exec_reset = cpu_reset, 892 .do_interrupt = loongarch_cpu_do_interrupt, 893 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 894 #endif 895 }; 896 #endif /* CONFIG_TCG */ 897 898 #ifndef CONFIG_USER_ONLY 899 #include "hw/core/sysemu-cpu-ops.h" 900 901 static const struct SysemuCPUOps loongarch_sysemu_ops = { 902 .has_work = loongarch_cpu_has_work, 903 .write_elf64_note = loongarch_cpu_write_elf64_note, 904 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 905 }; 906 907 static int64_t loongarch_cpu_get_arch_id(CPUState *cs) 908 { 909 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 910 911 return cpu->phy_id; 912 } 913 #endif 914 915 static const Property loongarch_cpu_properties[] = { 916 DEFINE_PROP_INT32("socket-id", LoongArchCPU, socket_id, 0), 917 DEFINE_PROP_INT32("core-id", LoongArchCPU, core_id, 0), 918 DEFINE_PROP_INT32("thread-id", LoongArchCPU, thread_id, 0), 919 DEFINE_PROP_INT32("node-id", LoongArchCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 920 }; 921 922 static void loongarch_cpu_class_init(ObjectClass *c, const void *data) 923 { 924 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 925 CPUClass *cc = CPU_CLASS(c); 926 DeviceClass *dc = DEVICE_CLASS(c); 927 ResettableClass *rc = RESETTABLE_CLASS(c); 928 929 device_class_set_props(dc, loongarch_cpu_properties); 930 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 931 &lacc->parent_realize); 932 device_class_set_parent_unrealize(dc, loongarch_cpu_unrealizefn, 933 &lacc->parent_unrealize); 934 resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL, 935 &lacc->parent_phases); 936 937 cc->class_by_name = loongarch_cpu_class_by_name; 938 cc->dump_state = loongarch_cpu_dump_state; 939 cc->set_pc = loongarch_cpu_set_pc; 940 cc->get_pc = loongarch_cpu_get_pc; 941 #ifndef CONFIG_USER_ONLY 942 cc->get_arch_id = loongarch_cpu_get_arch_id; 943 dc->vmsd = &vmstate_loongarch_cpu; 944 cc->sysemu_ops = &loongarch_sysemu_ops; 945 #endif 946 cc->disas_set_info = loongarch_cpu_disas_set_info; 947 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 948 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 949 cc->gdb_stop_before_watchpoint = true; 950 951 #ifdef CONFIG_TCG 952 cc->tcg_ops = &loongarch_tcg_ops; 953 #endif 954 dc->user_creatable = true; 955 } 956 957 static const gchar *loongarch32_gdb_arch_name(CPUState *cs) 958 { 959 return "loongarch32"; 960 } 961 962 static void loongarch32_cpu_class_init(ObjectClass *c, const void *data) 963 { 964 CPUClass *cc = CPU_CLASS(c); 965 966 cc->gdb_core_xml_file = "loongarch-base32.xml"; 967 cc->gdb_arch_name = loongarch32_gdb_arch_name; 968 } 969 970 static const gchar *loongarch64_gdb_arch_name(CPUState *cs) 971 { 972 return "loongarch64"; 973 } 974 975 static void loongarch64_cpu_class_init(ObjectClass *c, const void *data) 976 { 977 CPUClass *cc = CPU_CLASS(c); 978 979 cc->gdb_core_xml_file = "loongarch-base64.xml"; 980 cc->gdb_arch_name = loongarch64_gdb_arch_name; 981 } 982 983 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ 984 { \ 985 .parent = TYPE_LOONGARCH##size##_CPU, \ 986 .instance_init = initfn, \ 987 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 988 } 989 990 static const TypeInfo loongarch_cpu_type_infos[] = { 991 { 992 .name = TYPE_LOONGARCH_CPU, 993 .parent = TYPE_CPU, 994 .instance_size = sizeof(LoongArchCPU), 995 .instance_align = __alignof(LoongArchCPU), 996 .instance_init = loongarch_cpu_init, 997 998 .abstract = true, 999 .class_size = sizeof(LoongArchCPUClass), 1000 .class_init = loongarch_cpu_class_init, 1001 }, 1002 { 1003 .name = TYPE_LOONGARCH32_CPU, 1004 .parent = TYPE_LOONGARCH_CPU, 1005 1006 .abstract = true, 1007 .class_init = loongarch32_cpu_class_init, 1008 }, 1009 { 1010 .name = TYPE_LOONGARCH64_CPU, 1011 .parent = TYPE_LOONGARCH_CPU, 1012 1013 .abstract = true, 1014 .class_init = loongarch64_cpu_class_init, 1015 }, 1016 DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), 1017 DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), 1018 DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn), 1019 }; 1020 1021 DEFINE_TYPES(loongarch_cpu_type_infos) 1022