1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "system/qtest.h" 14 #include "system/tcg.h" 15 #include "system/kvm.h" 16 #include "kvm/kvm_loongarch.h" 17 #include "hw/qdev-properties.h" 18 #include "exec/exec-all.h" 19 #include "exec/translation-block.h" 20 #include "cpu.h" 21 #include "internals.h" 22 #include "fpu/softfloat-helpers.h" 23 #include "csr.h" 24 #ifndef CONFIG_USER_ONLY 25 #include "system/reset.h" 26 #endif 27 #include "vec.h" 28 #ifdef CONFIG_KVM 29 #include <linux/kvm.h> 30 #endif 31 #ifdef CONFIG_TCG 32 #include "exec/cpu_ldst.h" 33 #include "tcg/tcg.h" 34 #endif 35 36 const char * const regnames[32] = { 37 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 38 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 39 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 40 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 41 }; 42 43 const char * const fregnames[32] = { 44 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 45 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 46 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 47 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 48 }; 49 50 struct TypeExcp { 51 int32_t exccode; 52 const char * const name; 53 }; 54 55 static const struct TypeExcp excp_names[] = { 56 {EXCCODE_INT, "Interrupt"}, 57 {EXCCODE_PIL, "Page invalid exception for load"}, 58 {EXCCODE_PIS, "Page invalid exception for store"}, 59 {EXCCODE_PIF, "Page invalid exception for fetch"}, 60 {EXCCODE_PME, "Page modified exception"}, 61 {EXCCODE_PNR, "Page Not Readable exception"}, 62 {EXCCODE_PNX, "Page Not Executable exception"}, 63 {EXCCODE_PPI, "Page Privilege error"}, 64 {EXCCODE_ADEF, "Address error for instruction fetch"}, 65 {EXCCODE_ADEM, "Address error for Memory access"}, 66 {EXCCODE_SYS, "Syscall"}, 67 {EXCCODE_BRK, "Break"}, 68 {EXCCODE_INE, "Instruction Non-Existent"}, 69 {EXCCODE_IPE, "Instruction privilege error"}, 70 {EXCCODE_FPD, "Floating Point Disabled"}, 71 {EXCCODE_FPE, "Floating Point Exception"}, 72 {EXCCODE_DBP, "Debug breakpoint"}, 73 {EXCCODE_BCE, "Bound Check Exception"}, 74 {EXCCODE_SXD, "128 bit vector instructions Disable exception"}, 75 {EXCCODE_ASXD, "256 bit vector instructions Disable exception"}, 76 {EXCP_HLT, "EXCP_HLT"}, 77 }; 78 79 const char *loongarch_exception_name(int32_t exception) 80 { 81 int i; 82 83 for (i = 0; i < ARRAY_SIZE(excp_names); i++) { 84 if (excp_names[i].exccode == exception) { 85 return excp_names[i].name; 86 } 87 } 88 return "Unknown"; 89 } 90 91 void G_NORETURN do_raise_exception(CPULoongArchState *env, 92 uint32_t exception, 93 uintptr_t pc) 94 { 95 CPUState *cs = env_cpu(env); 96 97 qemu_log_mask(CPU_LOG_INT, "%s: exception: %d (%s)\n", 98 __func__, 99 exception, 100 loongarch_exception_name(exception)); 101 cs->exception_index = exception; 102 103 cpu_loop_exit_restore(cs, pc); 104 } 105 106 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 107 { 108 set_pc(cpu_env(cs), value); 109 } 110 111 static vaddr loongarch_cpu_get_pc(CPUState *cs) 112 { 113 return cpu_env(cs)->pc; 114 } 115 116 #ifndef CONFIG_USER_ONLY 117 #include "hw/loongarch/virt.h" 118 119 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 120 { 121 LoongArchCPU *cpu = opaque; 122 CPULoongArchState *env = &cpu->env; 123 CPUState *cs = CPU(cpu); 124 125 if (irq < 0 || irq >= N_IRQS) { 126 return; 127 } 128 129 if (kvm_enabled()) { 130 kvm_loongarch_set_interrupt(cpu, irq, level); 131 } else if (tcg_enabled()) { 132 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 133 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 134 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 135 } else { 136 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 137 } 138 } 139 } 140 141 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 142 { 143 bool ret = 0; 144 145 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 146 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 147 148 return ret; 149 } 150 151 /* Check if there is pending and not masked out interrupt */ 152 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 153 { 154 uint32_t pending; 155 uint32_t status; 156 157 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 158 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 159 160 return (pending & status) != 0; 161 } 162 #endif 163 164 #ifdef CONFIG_TCG 165 #ifndef CONFIG_USER_ONLY 166 static void loongarch_cpu_do_interrupt(CPUState *cs) 167 { 168 CPULoongArchState *env = cpu_env(cs); 169 bool update_badinstr = 1; 170 int cause = -1; 171 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 172 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 173 174 if (cs->exception_index != EXCCODE_INT) { 175 qemu_log_mask(CPU_LOG_INT, 176 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 177 " TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n", 178 __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA, 179 cs->exception_index, 180 loongarch_exception_name(cs->exception_index)); 181 } 182 183 switch (cs->exception_index) { 184 case EXCCODE_DBP: 185 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 186 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 187 goto set_DERA; 188 set_DERA: 189 env->CSR_DERA = env->pc; 190 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 191 set_pc(env, env->CSR_EENTRY + 0x480); 192 break; 193 case EXCCODE_INT: 194 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 195 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 196 goto set_DERA; 197 } 198 QEMU_FALLTHROUGH; 199 case EXCCODE_PIF: 200 case EXCCODE_ADEF: 201 cause = cs->exception_index; 202 update_badinstr = 0; 203 break; 204 case EXCCODE_SYS: 205 case EXCCODE_BRK: 206 case EXCCODE_INE: 207 case EXCCODE_IPE: 208 case EXCCODE_FPD: 209 case EXCCODE_FPE: 210 case EXCCODE_SXD: 211 case EXCCODE_ASXD: 212 env->CSR_BADV = env->pc; 213 QEMU_FALLTHROUGH; 214 case EXCCODE_BCE: 215 case EXCCODE_ADEM: 216 case EXCCODE_PIL: 217 case EXCCODE_PIS: 218 case EXCCODE_PME: 219 case EXCCODE_PNR: 220 case EXCCODE_PNX: 221 case EXCCODE_PPI: 222 cause = cs->exception_index; 223 break; 224 default: 225 qemu_log("Error: exception(%d) has not been supported\n", 226 cs->exception_index); 227 abort(); 228 } 229 230 if (update_badinstr) { 231 env->CSR_BADI = cpu_ldl_code(env, env->pc); 232 } 233 234 /* Save PLV and IE */ 235 if (tlbfill) { 236 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 237 FIELD_EX64(env->CSR_CRMD, 238 CSR_CRMD, PLV)); 239 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 240 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 241 /* set the DA mode */ 242 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 243 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 244 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 245 PC, (env->pc >> 2)); 246 } else { 247 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, 248 EXCODE_MCODE(cause)); 249 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, 250 EXCODE_SUBCODE(cause)); 251 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 252 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 253 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 254 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 255 env->CSR_ERA = env->pc; 256 } 257 258 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 259 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 260 261 if (vec_size) { 262 vec_size = (1 << vec_size) * 4; 263 } 264 265 if (cs->exception_index == EXCCODE_INT) { 266 /* Interrupt */ 267 uint32_t vector = 0; 268 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 269 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 270 271 /* Find the highest-priority interrupt. */ 272 vector = 31 - clz32(pending); 273 set_pc(env, env->CSR_EENTRY + \ 274 (EXCCODE_EXTERNAL_INT + vector) * vec_size); 275 qemu_log_mask(CPU_LOG_INT, 276 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 277 " cause %d\n" " A " TARGET_FMT_lx " D " 278 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 279 TARGET_FMT_lx "\n", 280 __func__, env->pc, env->CSR_ERA, 281 cause, env->CSR_BADV, env->CSR_DERA, vector, 282 env->CSR_ECFG, env->CSR_ESTAT); 283 } else { 284 if (tlbfill) { 285 set_pc(env, env->CSR_TLBRENTRY); 286 } else { 287 set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); 288 } 289 qemu_log_mask(CPU_LOG_INT, 290 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 291 " cause %d%s\n, ESTAT " TARGET_FMT_lx 292 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 293 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 294 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 295 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 296 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 297 env->CSR_ECFG, 298 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 299 env->CSR_BADI, env->gpr[11], cs->cpu_index, 300 env->CSR_ASID); 301 } 302 cs->exception_index = -1; 303 } 304 305 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 306 vaddr addr, unsigned size, 307 MMUAccessType access_type, 308 int mmu_idx, MemTxAttrs attrs, 309 MemTxResult response, 310 uintptr_t retaddr) 311 { 312 CPULoongArchState *env = cpu_env(cs); 313 314 if (access_type == MMU_INST_FETCH) { 315 do_raise_exception(env, EXCCODE_ADEF, retaddr); 316 } else { 317 do_raise_exception(env, EXCCODE_ADEM, retaddr); 318 } 319 } 320 321 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 322 { 323 if (interrupt_request & CPU_INTERRUPT_HARD) { 324 CPULoongArchState *env = cpu_env(cs); 325 326 if (cpu_loongarch_hw_interrupts_enabled(env) && 327 cpu_loongarch_hw_interrupts_pending(env)) { 328 /* Raise it */ 329 cs->exception_index = EXCCODE_INT; 330 loongarch_cpu_do_interrupt(cs); 331 return true; 332 } 333 } 334 return false; 335 } 336 #endif 337 338 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 339 const TranslationBlock *tb) 340 { 341 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 342 set_pc(cpu_env(cs), tb->pc); 343 } 344 345 static void loongarch_restore_state_to_opc(CPUState *cs, 346 const TranslationBlock *tb, 347 const uint64_t *data) 348 { 349 set_pc(cpu_env(cs), data[0]); 350 } 351 #endif /* CONFIG_TCG */ 352 353 static bool loongarch_cpu_has_work(CPUState *cs) 354 { 355 #ifdef CONFIG_USER_ONLY 356 return true; 357 #else 358 bool has_work = false; 359 360 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 361 cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) { 362 has_work = true; 363 } 364 365 return has_work; 366 #endif 367 } 368 369 static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) 370 { 371 CPULoongArchState *env = cpu_env(cs); 372 373 if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { 374 return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); 375 } 376 return MMU_DA_IDX; 377 } 378 379 static void loongarch_la464_init_csr(Object *obj) 380 { 381 #ifndef CONFIG_USER_ONLY 382 static bool initialized; 383 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 384 CPULoongArchState *env = &cpu->env; 385 int i, num; 386 387 if (!initialized) { 388 initialized = true; 389 num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM); 390 for (i = num; i < 16; i++) { 391 set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED); 392 } 393 set_csr_flag(LOONGARCH_CSR_IMPCTL1, CSRFL_UNUSED); 394 set_csr_flag(LOONGARCH_CSR_IMPCTL2, CSRFL_UNUSED); 395 set_csr_flag(LOONGARCH_CSR_MERRCTL, CSRFL_UNUSED); 396 set_csr_flag(LOONGARCH_CSR_MERRINFO1, CSRFL_UNUSED); 397 set_csr_flag(LOONGARCH_CSR_MERRINFO2, CSRFL_UNUSED); 398 set_csr_flag(LOONGARCH_CSR_MERRENTRY, CSRFL_UNUSED); 399 set_csr_flag(LOONGARCH_CSR_MERRERA, CSRFL_UNUSED); 400 set_csr_flag(LOONGARCH_CSR_MERRSAVE, CSRFL_UNUSED); 401 set_csr_flag(LOONGARCH_CSR_CTAG, CSRFL_UNUSED); 402 } 403 #endif 404 } 405 406 static void loongarch_la464_initfn(Object *obj) 407 { 408 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 409 CPULoongArchState *env = &cpu->env; 410 uint32_t data = 0, field; 411 int i; 412 413 for (i = 0; i < 21; i++) { 414 env->cpucfg[i] = 0x0; 415 } 416 417 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; 418 env->cpucfg[0] = 0x14c010; /* PRID */ 419 420 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 421 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 422 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 423 if (kvm_enabled()) { 424 /* GPA address width of VM is 47, field value is 47 - 1 */ 425 field = 0x2e; 426 } else { 427 field = 0x2f; /* 48 bit - 1 */ 428 } 429 data = FIELD_DP32(data, CPUCFG1, PALEN, field); 430 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 431 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 432 data = FIELD_DP32(data, CPUCFG1, RI, 1); 433 data = FIELD_DP32(data, CPUCFG1, EP, 1); 434 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 435 data = FIELD_DP32(data, CPUCFG1, HP, 1); 436 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 437 env->cpucfg[1] = data; 438 439 data = 0; 440 data = FIELD_DP32(data, CPUCFG2, FP, 1); 441 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 442 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 443 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 444 data = FIELD_DP32(data, CPUCFG2, LSX, 1), 445 data = FIELD_DP32(data, CPUCFG2, LASX, 1), 446 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 447 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 448 data = FIELD_DP32(data, CPUCFG2, LSPW, 1); 449 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 450 env->cpucfg[2] = data; 451 452 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 453 454 data = 0; 455 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 456 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 457 env->cpucfg[5] = data; 458 459 data = 0; 460 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 461 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 462 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 463 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 464 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 465 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 466 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 467 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 468 env->cpucfg[16] = data; 469 470 data = 0; 471 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 472 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 473 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 474 env->cpucfg[17] = data; 475 476 data = 0; 477 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 478 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 479 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 480 env->cpucfg[18] = data; 481 482 data = 0; 483 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 484 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 485 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 486 env->cpucfg[19] = data; 487 488 data = 0; 489 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 490 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 491 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); 492 env->cpucfg[20] = data; 493 494 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 495 496 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, 8); 497 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS, 0x2f); 498 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 7); 499 500 env->CSR_PRCFG2 = 0x3ffff000; 501 502 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 503 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 504 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 505 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 506 507 loongarch_la464_init_csr(obj); 508 loongarch_cpu_post_init(obj); 509 } 510 511 static void loongarch_la132_initfn(Object *obj) 512 { 513 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 514 CPULoongArchState *env = &cpu->env; 515 uint32_t data = 0; 516 int i; 517 518 for (i = 0; i < 21; i++) { 519 env->cpucfg[i] = 0x0; 520 } 521 522 cpu->dtb_compatible = "loongarch,Loongson-1C103"; 523 env->cpucfg[0] = 0x148042; /* PRID */ 524 525 data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ 526 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 527 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 528 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ 529 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ 530 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 531 data = FIELD_DP32(data, CPUCFG1, RI, 0); 532 data = FIELD_DP32(data, CPUCFG1, EP, 0); 533 data = FIELD_DP32(data, CPUCFG1, RPLV, 0); 534 data = FIELD_DP32(data, CPUCFG1, HP, 1); 535 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 536 env->cpucfg[1] = data; 537 } 538 539 static void loongarch_max_initfn(Object *obj) 540 { 541 /* '-cpu max' for TCG: we use cpu la464. */ 542 loongarch_la464_initfn(obj); 543 } 544 545 static void loongarch_cpu_reset_hold(Object *obj, ResetType type) 546 { 547 CPUState *cs = CPU(obj); 548 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(obj); 549 CPULoongArchState *env = cpu_env(cs); 550 551 if (lacc->parent_phases.hold) { 552 lacc->parent_phases.hold(obj, type); 553 } 554 555 #ifdef CONFIG_TCG 556 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 557 #endif 558 env->fcsr0 = 0x0; 559 560 int n; 561 /* Set csr registers value after reset, see the manual 6.4. */ 562 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 563 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 564 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 565 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 566 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 0); 567 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 0); 568 569 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 570 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 571 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 572 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 573 574 env->CSR_MISC = 0; 575 576 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 577 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 578 579 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 580 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 581 env->CSR_CPUID = cs->cpu_index; 582 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 583 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 584 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 585 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 586 env->CSR_TID = cs->cpu_index; 587 /* 588 * Workaround for edk2-stable202408, CSR PGD register is set only if 589 * its value is equal to zero for boot cpu, it causes reboot issue. 590 * 591 * Here clear CSR registers relative with TLB. 592 */ 593 env->CSR_PGDH = 0; 594 env->CSR_PGDL = 0; 595 env->CSR_PWCL = 0; 596 env->CSR_PWCH = 0; 597 env->CSR_STLBPS = 0; 598 env->CSR_EENTRY = 0; 599 env->CSR_TLBRENTRY = 0; 600 env->CSR_MERRENTRY = 0; 601 602 for (n = 0; n < 4; n++) { 603 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 604 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 605 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 606 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 607 } 608 609 #ifndef CONFIG_USER_ONLY 610 env->pc = 0x1c000000; 611 #ifdef CONFIG_TCG 612 memset(env->tlb, 0, sizeof(env->tlb)); 613 #endif 614 if (kvm_enabled()) { 615 kvm_arch_reset_vcpu(cs); 616 } 617 #endif 618 619 #ifdef CONFIG_TCG 620 restore_fp_status(env); 621 #endif 622 cs->exception_index = -1; 623 } 624 625 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 626 { 627 info->endian = BFD_ENDIAN_LITTLE; 628 info->print_insn = print_insn_loongarch; 629 } 630 631 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 632 { 633 CPUState *cs = CPU(dev); 634 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 635 Error *local_err = NULL; 636 637 cpu_exec_realizefn(cs, &local_err); 638 if (local_err != NULL) { 639 error_propagate(errp, local_err); 640 return; 641 } 642 643 loongarch_cpu_register_gdb_regs_for_features(cs); 644 645 qemu_init_vcpu(cs); 646 cpu_reset(cs); 647 648 lacc->parent_realize(dev, errp); 649 } 650 651 static void loongarch_cpu_unrealizefn(DeviceState *dev) 652 { 653 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 654 655 #ifndef CONFIG_USER_ONLY 656 cpu_remove_sync(CPU(dev)); 657 #endif 658 659 lacc->parent_unrealize(dev); 660 } 661 662 static bool loongarch_get_lsx(Object *obj, Error **errp) 663 { 664 return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF; 665 } 666 667 static void loongarch_set_lsx(Object *obj, bool value, Error **errp) 668 { 669 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 670 uint32_t val; 671 672 cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 673 if (cpu->lsx == ON_OFF_AUTO_OFF) { 674 cpu->lasx = ON_OFF_AUTO_OFF; 675 if (cpu->lasx == ON_OFF_AUTO_ON) { 676 error_setg(errp, "Failed to disable LSX since LASX is enabled"); 677 return; 678 } 679 } 680 681 if (kvm_enabled()) { 682 /* kvm feature detection in function kvm_arch_init_vcpu */ 683 return; 684 } 685 686 /* LSX feature detection in TCG mode */ 687 val = cpu->env.cpucfg[2]; 688 if (cpu->lsx == ON_OFF_AUTO_ON) { 689 if (FIELD_EX32(val, CPUCFG2, LSX) == 0) { 690 error_setg(errp, "Failed to enable LSX in TCG mode"); 691 return; 692 } 693 } else { 694 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0); 695 val = cpu->env.cpucfg[2]; 696 } 697 698 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value); 699 } 700 701 static bool loongarch_get_lasx(Object *obj, Error **errp) 702 { 703 return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF; 704 } 705 706 static void loongarch_set_lasx(Object *obj, bool value, Error **errp) 707 { 708 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 709 uint32_t val; 710 711 cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 712 if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) { 713 error_setg(errp, "Failed to enable LASX since lSX is disabled"); 714 return; 715 } 716 717 if (kvm_enabled()) { 718 /* kvm feature detection in function kvm_arch_init_vcpu */ 719 return; 720 } 721 722 /* LASX feature detection in TCG mode */ 723 val = cpu->env.cpucfg[2]; 724 if (cpu->lasx == ON_OFF_AUTO_ON) { 725 if (FIELD_EX32(val, CPUCFG2, LASX) == 0) { 726 error_setg(errp, "Failed to enable LASX in TCG mode"); 727 return; 728 } 729 } 730 731 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value); 732 } 733 734 void loongarch_cpu_post_init(Object *obj) 735 { 736 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 737 738 cpu->lbt = ON_OFF_AUTO_OFF; 739 cpu->pmu = ON_OFF_AUTO_OFF; 740 cpu->lsx = ON_OFF_AUTO_AUTO; 741 cpu->lasx = ON_OFF_AUTO_AUTO; 742 object_property_add_bool(obj, "lsx", loongarch_get_lsx, 743 loongarch_set_lsx); 744 object_property_add_bool(obj, "lasx", loongarch_get_lasx, 745 loongarch_set_lasx); 746 /* lbt is enabled only in kvm mode, not supported in tcg mode */ 747 if (kvm_enabled()) { 748 kvm_loongarch_cpu_post_init(cpu); 749 } 750 } 751 752 static void loongarch_cpu_init(Object *obj) 753 { 754 #ifndef CONFIG_USER_ONLY 755 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 756 757 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 758 #ifdef CONFIG_TCG 759 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 760 &loongarch_constant_timer_cb, cpu); 761 #endif 762 #endif 763 } 764 765 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 766 { 767 ObjectClass *oc; 768 769 oc = object_class_by_name(cpu_model); 770 if (!oc) { 771 g_autofree char *typename 772 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 773 oc = object_class_by_name(typename); 774 } 775 776 return oc; 777 } 778 779 static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f) 780 { 781 #ifndef CONFIG_USER_ONLY 782 CPULoongArchState *env = cpu_env(cs); 783 CSRInfo *csr_info; 784 int64_t *addr; 785 int i, j, len, col = 0; 786 787 qemu_fprintf(f, "\n"); 788 789 /* Dump all generic CSR register */ 790 for (i = 0; i < LOONGARCH_CSR_DBG; i++) { 791 csr_info = get_csr(i); 792 if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) { 793 if (i == (col + 3)) { 794 qemu_fprintf(f, "\n"); 795 } 796 797 continue; 798 } 799 800 if ((i > (col + 3)) || (i == col)) { 801 col = i & ~3; 802 qemu_fprintf(f, " CSR%03d:", col); 803 } 804 805 addr = (void *)env + csr_info->offset; 806 qemu_fprintf(f, " %s ", csr_info->name); 807 len = strlen(csr_info->name); 808 for (; len < 6; len++) { 809 qemu_fprintf(f, " "); 810 } 811 812 qemu_fprintf(f, "%" PRIx64, *addr); 813 j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1); 814 len += j / 4 + 1; 815 for (; len < 22; len++) { 816 qemu_fprintf(f, " "); 817 } 818 819 if (i == (col + 3)) { 820 qemu_fprintf(f, "\n"); 821 } 822 } 823 qemu_fprintf(f, "\n"); 824 #endif 825 } 826 827 static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 828 { 829 CPULoongArchState *env = cpu_env(cs); 830 int i; 831 832 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 833 qemu_fprintf(f, " FCSR0 0x%08x\n", env->fcsr0); 834 835 /* gpr */ 836 for (i = 0; i < 32; i++) { 837 if ((i & 3) == 0) { 838 qemu_fprintf(f, " GPR%02d:", i); 839 } 840 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 841 if ((i & 3) == 3) { 842 qemu_fprintf(f, "\n"); 843 } 844 } 845 846 /* csr */ 847 loongarch_cpu_dump_csr(cs, f); 848 849 /* fpr */ 850 if (flags & CPU_DUMP_FPU) { 851 for (i = 0; i < 32; i++) { 852 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i].vreg.D(0)); 853 if ((i & 3) == 3) { 854 qemu_fprintf(f, "\n"); 855 } 856 } 857 } 858 } 859 860 #ifdef CONFIG_TCG 861 #include "accel/tcg/cpu-ops.h" 862 863 static const TCGCPUOps loongarch_tcg_ops = { 864 .initialize = loongarch_translate_init, 865 .translate_code = loongarch_translate_code, 866 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 867 .restore_state_to_opc = loongarch_restore_state_to_opc, 868 869 #ifndef CONFIG_USER_ONLY 870 .tlb_fill = loongarch_cpu_tlb_fill, 871 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 872 .cpu_exec_halt = loongarch_cpu_has_work, 873 .do_interrupt = loongarch_cpu_do_interrupt, 874 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 875 #endif 876 }; 877 #endif /* CONFIG_TCG */ 878 879 #ifndef CONFIG_USER_ONLY 880 #include "hw/core/sysemu-cpu-ops.h" 881 882 static const struct SysemuCPUOps loongarch_sysemu_ops = { 883 .write_elf64_note = loongarch_cpu_write_elf64_note, 884 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 885 }; 886 887 static int64_t loongarch_cpu_get_arch_id(CPUState *cs) 888 { 889 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 890 891 return cpu->phy_id; 892 } 893 #endif 894 895 static const Property loongarch_cpu_properties[] = { 896 DEFINE_PROP_INT32("socket-id", LoongArchCPU, socket_id, 0), 897 DEFINE_PROP_INT32("core-id", LoongArchCPU, core_id, 0), 898 DEFINE_PROP_INT32("thread-id", LoongArchCPU, thread_id, 0), 899 DEFINE_PROP_INT32("node-id", LoongArchCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 900 }; 901 902 static void loongarch_cpu_class_init(ObjectClass *c, void *data) 903 { 904 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 905 CPUClass *cc = CPU_CLASS(c); 906 DeviceClass *dc = DEVICE_CLASS(c); 907 ResettableClass *rc = RESETTABLE_CLASS(c); 908 909 device_class_set_props(dc, loongarch_cpu_properties); 910 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 911 &lacc->parent_realize); 912 device_class_set_parent_unrealize(dc, loongarch_cpu_unrealizefn, 913 &lacc->parent_unrealize); 914 resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL, 915 &lacc->parent_phases); 916 917 cc->class_by_name = loongarch_cpu_class_by_name; 918 cc->has_work = loongarch_cpu_has_work; 919 cc->mmu_index = loongarch_cpu_mmu_index; 920 cc->dump_state = loongarch_cpu_dump_state; 921 cc->set_pc = loongarch_cpu_set_pc; 922 cc->get_pc = loongarch_cpu_get_pc; 923 #ifndef CONFIG_USER_ONLY 924 cc->get_arch_id = loongarch_cpu_get_arch_id; 925 dc->vmsd = &vmstate_loongarch_cpu; 926 cc->sysemu_ops = &loongarch_sysemu_ops; 927 #endif 928 cc->disas_set_info = loongarch_cpu_disas_set_info; 929 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 930 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 931 cc->gdb_stop_before_watchpoint = true; 932 933 #ifdef CONFIG_TCG 934 cc->tcg_ops = &loongarch_tcg_ops; 935 #endif 936 dc->user_creatable = true; 937 } 938 939 static const gchar *loongarch32_gdb_arch_name(CPUState *cs) 940 { 941 return "loongarch32"; 942 } 943 944 static void loongarch32_cpu_class_init(ObjectClass *c, void *data) 945 { 946 CPUClass *cc = CPU_CLASS(c); 947 948 cc->gdb_core_xml_file = "loongarch-base32.xml"; 949 cc->gdb_arch_name = loongarch32_gdb_arch_name; 950 } 951 952 static const gchar *loongarch64_gdb_arch_name(CPUState *cs) 953 { 954 return "loongarch64"; 955 } 956 957 static void loongarch64_cpu_class_init(ObjectClass *c, void *data) 958 { 959 CPUClass *cc = CPU_CLASS(c); 960 961 cc->gdb_core_xml_file = "loongarch-base64.xml"; 962 cc->gdb_arch_name = loongarch64_gdb_arch_name; 963 } 964 965 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ 966 { \ 967 .parent = TYPE_LOONGARCH##size##_CPU, \ 968 .instance_init = initfn, \ 969 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 970 } 971 972 static const TypeInfo loongarch_cpu_type_infos[] = { 973 { 974 .name = TYPE_LOONGARCH_CPU, 975 .parent = TYPE_CPU, 976 .instance_size = sizeof(LoongArchCPU), 977 .instance_align = __alignof(LoongArchCPU), 978 .instance_init = loongarch_cpu_init, 979 980 .abstract = true, 981 .class_size = sizeof(LoongArchCPUClass), 982 .class_init = loongarch_cpu_class_init, 983 }, 984 { 985 .name = TYPE_LOONGARCH32_CPU, 986 .parent = TYPE_LOONGARCH_CPU, 987 988 .abstract = true, 989 .class_init = loongarch32_cpu_class_init, 990 }, 991 { 992 .name = TYPE_LOONGARCH64_CPU, 993 .parent = TYPE_LOONGARCH_CPU, 994 995 .abstract = true, 996 .class_init = loongarch64_cpu_class_init, 997 }, 998 DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), 999 DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), 1000 DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn), 1001 }; 1002 1003 DEFINE_TYPES(loongarch_cpu_type_infos) 1004