1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "system/qtest.h" 14 #include "system/tcg.h" 15 #include "system/kvm.h" 16 #include "kvm/kvm_loongarch.h" 17 #include "hw/qdev-properties.h" 18 #include "exec/exec-all.h" 19 #include "exec/translation-block.h" 20 #include "cpu.h" 21 #include "internals.h" 22 #include "fpu/softfloat-helpers.h" 23 #include "csr.h" 24 #ifndef CONFIG_USER_ONLY 25 #include "system/reset.h" 26 #endif 27 #include "vec.h" 28 #ifdef CONFIG_KVM 29 #include <linux/kvm.h> 30 #endif 31 #ifdef CONFIG_TCG 32 #include "accel/tcg/cpu-ldst.h" 33 #include "tcg/tcg.h" 34 #endif 35 #include "tcg/tcg_loongarch.h" 36 37 const char * const regnames[32] = { 38 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 39 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 40 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 41 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 42 }; 43 44 const char * const fregnames[32] = { 45 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 46 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 47 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 48 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 49 }; 50 51 struct TypeExcp { 52 int32_t exccode; 53 const char * const name; 54 }; 55 56 static const struct TypeExcp excp_names[] = { 57 {EXCCODE_INT, "Interrupt"}, 58 {EXCCODE_PIL, "Page invalid exception for load"}, 59 {EXCCODE_PIS, "Page invalid exception for store"}, 60 {EXCCODE_PIF, "Page invalid exception for fetch"}, 61 {EXCCODE_PME, "Page modified exception"}, 62 {EXCCODE_PNR, "Page Not Readable exception"}, 63 {EXCCODE_PNX, "Page Not Executable exception"}, 64 {EXCCODE_PPI, "Page Privilege error"}, 65 {EXCCODE_ADEF, "Address error for instruction fetch"}, 66 {EXCCODE_ADEM, "Address error for Memory access"}, 67 {EXCCODE_SYS, "Syscall"}, 68 {EXCCODE_BRK, "Break"}, 69 {EXCCODE_INE, "Instruction Non-Existent"}, 70 {EXCCODE_IPE, "Instruction privilege error"}, 71 {EXCCODE_FPD, "Floating Point Disabled"}, 72 {EXCCODE_FPE, "Floating Point Exception"}, 73 {EXCCODE_DBP, "Debug breakpoint"}, 74 {EXCCODE_BCE, "Bound Check Exception"}, 75 {EXCCODE_SXD, "128 bit vector instructions Disable exception"}, 76 {EXCCODE_ASXD, "256 bit vector instructions Disable exception"}, 77 {EXCP_HLT, "EXCP_HLT"}, 78 }; 79 80 const char *loongarch_exception_name(int32_t exception) 81 { 82 int i; 83 84 for (i = 0; i < ARRAY_SIZE(excp_names); i++) { 85 if (excp_names[i].exccode == exception) { 86 return excp_names[i].name; 87 } 88 } 89 return "Unknown"; 90 } 91 92 void G_NORETURN do_raise_exception(CPULoongArchState *env, 93 uint32_t exception, 94 uintptr_t pc) 95 { 96 CPUState *cs = env_cpu(env); 97 98 qemu_log_mask(CPU_LOG_INT, "%s: exception: %d (%s)\n", 99 __func__, 100 exception, 101 loongarch_exception_name(exception)); 102 cs->exception_index = exception; 103 104 cpu_loop_exit_restore(cs, pc); 105 } 106 107 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 108 { 109 set_pc(cpu_env(cs), value); 110 } 111 112 static vaddr loongarch_cpu_get_pc(CPUState *cs) 113 { 114 return cpu_env(cs)->pc; 115 } 116 117 #ifndef CONFIG_USER_ONLY 118 #include "hw/loongarch/virt.h" 119 120 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 121 { 122 LoongArchCPU *cpu = opaque; 123 CPULoongArchState *env = &cpu->env; 124 CPUState *cs = CPU(cpu); 125 126 if (irq < 0 || irq >= N_IRQS) { 127 return; 128 } 129 130 if (kvm_enabled()) { 131 kvm_loongarch_set_interrupt(cpu, irq, level); 132 } else if (tcg_enabled()) { 133 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 134 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 135 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 136 } else { 137 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 138 } 139 } 140 } 141 142 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 143 { 144 bool ret = 0; 145 146 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 147 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 148 149 return ret; 150 } 151 152 /* Check if there is pending and not masked out interrupt */ 153 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 154 { 155 uint32_t pending; 156 uint32_t status; 157 158 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 159 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 160 161 return (pending & status) != 0; 162 } 163 #endif 164 165 #ifdef CONFIG_TCG 166 #ifndef CONFIG_USER_ONLY 167 static void loongarch_cpu_do_interrupt(CPUState *cs) 168 { 169 CPULoongArchState *env = cpu_env(cs); 170 bool update_badinstr = 1; 171 int cause = -1; 172 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 173 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 174 175 if (cs->exception_index != EXCCODE_INT) { 176 qemu_log_mask(CPU_LOG_INT, 177 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 178 " TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n", 179 __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA, 180 cs->exception_index, 181 loongarch_exception_name(cs->exception_index)); 182 } 183 184 switch (cs->exception_index) { 185 case EXCCODE_DBP: 186 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 187 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 188 goto set_DERA; 189 set_DERA: 190 env->CSR_DERA = env->pc; 191 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 192 set_pc(env, env->CSR_EENTRY + 0x480); 193 break; 194 case EXCCODE_INT: 195 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 196 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 197 goto set_DERA; 198 } 199 QEMU_FALLTHROUGH; 200 case EXCCODE_PIF: 201 case EXCCODE_ADEF: 202 cause = cs->exception_index; 203 update_badinstr = 0; 204 break; 205 case EXCCODE_SYS: 206 case EXCCODE_BRK: 207 case EXCCODE_INE: 208 case EXCCODE_IPE: 209 case EXCCODE_FPD: 210 case EXCCODE_FPE: 211 case EXCCODE_SXD: 212 case EXCCODE_ASXD: 213 env->CSR_BADV = env->pc; 214 QEMU_FALLTHROUGH; 215 case EXCCODE_BCE: 216 case EXCCODE_ADEM: 217 case EXCCODE_PIL: 218 case EXCCODE_PIS: 219 case EXCCODE_PME: 220 case EXCCODE_PNR: 221 case EXCCODE_PNX: 222 case EXCCODE_PPI: 223 cause = cs->exception_index; 224 break; 225 default: 226 qemu_log("Error: exception(%d) has not been supported\n", 227 cs->exception_index); 228 abort(); 229 } 230 231 if (update_badinstr) { 232 env->CSR_BADI = cpu_ldl_code(env, env->pc); 233 } 234 235 /* Save PLV and IE */ 236 if (tlbfill) { 237 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 238 FIELD_EX64(env->CSR_CRMD, 239 CSR_CRMD, PLV)); 240 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 241 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 242 /* set the DA mode */ 243 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 244 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 245 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 246 PC, (env->pc >> 2)); 247 } else { 248 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, 249 EXCODE_MCODE(cause)); 250 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, 251 EXCODE_SUBCODE(cause)); 252 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 253 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 254 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 255 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 256 env->CSR_ERA = env->pc; 257 } 258 259 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 260 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 261 262 if (vec_size) { 263 vec_size = (1 << vec_size) * 4; 264 } 265 266 if (cs->exception_index == EXCCODE_INT) { 267 /* Interrupt */ 268 uint32_t vector = 0; 269 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 270 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 271 272 /* Find the highest-priority interrupt. */ 273 vector = 31 - clz32(pending); 274 set_pc(env, env->CSR_EENTRY + \ 275 (EXCCODE_EXTERNAL_INT + vector) * vec_size); 276 qemu_log_mask(CPU_LOG_INT, 277 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 278 " cause %d\n" " A " TARGET_FMT_lx " D " 279 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 280 TARGET_FMT_lx "\n", 281 __func__, env->pc, env->CSR_ERA, 282 cause, env->CSR_BADV, env->CSR_DERA, vector, 283 env->CSR_ECFG, env->CSR_ESTAT); 284 } else { 285 if (tlbfill) { 286 set_pc(env, env->CSR_TLBRENTRY); 287 } else { 288 set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); 289 } 290 qemu_log_mask(CPU_LOG_INT, 291 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 292 " cause %d%s\n, ESTAT " TARGET_FMT_lx 293 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 294 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 295 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 296 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 297 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 298 env->CSR_ECFG, 299 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 300 env->CSR_BADI, env->gpr[11], cs->cpu_index, 301 env->CSR_ASID); 302 } 303 cs->exception_index = -1; 304 } 305 306 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 307 vaddr addr, unsigned size, 308 MMUAccessType access_type, 309 int mmu_idx, MemTxAttrs attrs, 310 MemTxResult response, 311 uintptr_t retaddr) 312 { 313 CPULoongArchState *env = cpu_env(cs); 314 315 if (access_type == MMU_INST_FETCH) { 316 do_raise_exception(env, EXCCODE_ADEF, retaddr); 317 } else { 318 do_raise_exception(env, EXCCODE_ADEM, retaddr); 319 } 320 } 321 322 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 323 { 324 if (interrupt_request & CPU_INTERRUPT_HARD) { 325 CPULoongArchState *env = cpu_env(cs); 326 327 if (cpu_loongarch_hw_interrupts_enabled(env) && 328 cpu_loongarch_hw_interrupts_pending(env)) { 329 /* Raise it */ 330 cs->exception_index = EXCCODE_INT; 331 loongarch_cpu_do_interrupt(cs); 332 return true; 333 } 334 } 335 return false; 336 } 337 #endif 338 339 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 340 const TranslationBlock *tb) 341 { 342 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 343 set_pc(cpu_env(cs), tb->pc); 344 } 345 346 static void loongarch_restore_state_to_opc(CPUState *cs, 347 const TranslationBlock *tb, 348 const uint64_t *data) 349 { 350 set_pc(cpu_env(cs), data[0]); 351 } 352 #endif /* CONFIG_TCG */ 353 354 #ifndef CONFIG_USER_ONLY 355 static bool loongarch_cpu_has_work(CPUState *cs) 356 { 357 bool has_work = false; 358 359 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 360 cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) { 361 has_work = true; 362 } 363 364 return has_work; 365 } 366 #endif /* !CONFIG_USER_ONLY */ 367 368 static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) 369 { 370 CPULoongArchState *env = cpu_env(cs); 371 372 if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { 373 return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); 374 } 375 return MMU_DA_IDX; 376 } 377 378 static void loongarch_la464_init_csr(Object *obj) 379 { 380 #ifndef CONFIG_USER_ONLY 381 static bool initialized; 382 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 383 CPULoongArchState *env = &cpu->env; 384 int i, num; 385 386 if (!initialized) { 387 initialized = true; 388 num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM); 389 for (i = num; i < 16; i++) { 390 set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED); 391 } 392 set_csr_flag(LOONGARCH_CSR_IMPCTL1, CSRFL_UNUSED); 393 set_csr_flag(LOONGARCH_CSR_IMPCTL2, CSRFL_UNUSED); 394 set_csr_flag(LOONGARCH_CSR_MERRCTL, CSRFL_UNUSED); 395 set_csr_flag(LOONGARCH_CSR_MERRINFO1, CSRFL_UNUSED); 396 set_csr_flag(LOONGARCH_CSR_MERRINFO2, CSRFL_UNUSED); 397 set_csr_flag(LOONGARCH_CSR_MERRENTRY, CSRFL_UNUSED); 398 set_csr_flag(LOONGARCH_CSR_MERRERA, CSRFL_UNUSED); 399 set_csr_flag(LOONGARCH_CSR_MERRSAVE, CSRFL_UNUSED); 400 set_csr_flag(LOONGARCH_CSR_CTAG, CSRFL_UNUSED); 401 } 402 #endif 403 } 404 405 static void loongarch_la464_initfn(Object *obj) 406 { 407 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 408 CPULoongArchState *env = &cpu->env; 409 uint32_t data = 0, field; 410 int i; 411 412 for (i = 0; i < 21; i++) { 413 env->cpucfg[i] = 0x0; 414 } 415 416 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; 417 env->cpucfg[0] = 0x14c010; /* PRID */ 418 419 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 420 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 421 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 422 if (kvm_enabled()) { 423 /* GPA address width of VM is 47, field value is 47 - 1 */ 424 field = 0x2e; 425 } else { 426 field = 0x2f; /* 48 bit - 1 */ 427 } 428 data = FIELD_DP32(data, CPUCFG1, PALEN, field); 429 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 430 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 431 data = FIELD_DP32(data, CPUCFG1, RI, 1); 432 data = FIELD_DP32(data, CPUCFG1, EP, 1); 433 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 434 data = FIELD_DP32(data, CPUCFG1, HP, 1); 435 data = FIELD_DP32(data, CPUCFG1, CRC, 1); 436 env->cpucfg[1] = data; 437 438 data = 0; 439 data = FIELD_DP32(data, CPUCFG2, FP, 1); 440 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 441 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 442 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 443 data = FIELD_DP32(data, CPUCFG2, LSX, 1), 444 data = FIELD_DP32(data, CPUCFG2, LASX, 1), 445 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 446 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 447 data = FIELD_DP32(data, CPUCFG2, LSPW, 1); 448 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 449 env->cpucfg[2] = data; 450 451 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 452 453 data = 0; 454 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 455 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 456 env->cpucfg[5] = data; 457 458 data = 0; 459 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 460 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 461 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 462 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 463 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 464 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 465 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 466 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 467 env->cpucfg[16] = data; 468 469 data = 0; 470 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 471 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 472 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 473 env->cpucfg[17] = data; 474 475 data = 0; 476 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 477 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 478 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 479 env->cpucfg[18] = data; 480 481 data = 0; 482 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 483 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 484 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 485 env->cpucfg[19] = data; 486 487 data = 0; 488 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 489 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 490 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); 491 env->cpucfg[20] = data; 492 493 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 494 495 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, 8); 496 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS, 0x2f); 497 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 7); 498 499 env->CSR_PRCFG2 = 0x3ffff000; 500 501 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 502 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 503 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 504 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 505 506 loongarch_la464_init_csr(obj); 507 loongarch_cpu_post_init(obj); 508 } 509 510 static void loongarch_la132_initfn(Object *obj) 511 { 512 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 513 CPULoongArchState *env = &cpu->env; 514 uint32_t data = 0; 515 int i; 516 517 for (i = 0; i < 21; i++) { 518 env->cpucfg[i] = 0x0; 519 } 520 521 cpu->dtb_compatible = "loongarch,Loongson-1C103"; 522 env->cpucfg[0] = 0x148042; /* PRID */ 523 524 data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ 525 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 526 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 527 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ 528 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ 529 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 530 data = FIELD_DP32(data, CPUCFG1, RI, 0); 531 data = FIELD_DP32(data, CPUCFG1, EP, 0); 532 data = FIELD_DP32(data, CPUCFG1, RPLV, 0); 533 data = FIELD_DP32(data, CPUCFG1, HP, 1); 534 data = FIELD_DP32(data, CPUCFG1, CRC, 1); 535 env->cpucfg[1] = data; 536 } 537 538 static void loongarch_max_initfn(Object *obj) 539 { 540 /* '-cpu max' for TCG: we use cpu la464. */ 541 loongarch_la464_initfn(obj); 542 } 543 544 static void loongarch_cpu_reset_hold(Object *obj, ResetType type) 545 { 546 uint8_t tlb_ps; 547 CPUState *cs = CPU(obj); 548 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(obj); 549 CPULoongArchState *env = cpu_env(cs); 550 551 if (lacc->parent_phases.hold) { 552 lacc->parent_phases.hold(obj, type); 553 } 554 555 #ifdef CONFIG_TCG 556 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 557 #endif 558 env->fcsr0 = 0x0; 559 560 int n; 561 /* Set csr registers value after reset, see the manual 6.4. */ 562 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 563 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 564 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 565 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 566 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 0); 567 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 0); 568 569 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 570 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 571 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 572 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 573 574 env->CSR_MISC = 0; 575 576 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 577 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 578 579 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 580 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 581 env->CSR_CPUID = cs->cpu_index; 582 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 583 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 584 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 585 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 586 env->CSR_TID = cs->cpu_index; 587 /* 588 * Workaround for edk2-stable202408, CSR PGD register is set only if 589 * its value is equal to zero for boot cpu, it causes reboot issue. 590 * 591 * Here clear CSR registers relative with TLB. 592 */ 593 env->CSR_PGDH = 0; 594 env->CSR_PGDL = 0; 595 env->CSR_PWCH = 0; 596 env->CSR_EENTRY = 0; 597 env->CSR_TLBRENTRY = 0; 598 env->CSR_MERRENTRY = 0; 599 /* set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits from CSR_PRCFG2 */ 600 if (env->CSR_PRCFG2 == 0) { 601 env->CSR_PRCFG2 = 0x3fffff000; 602 } 603 tlb_ps = ctz32(env->CSR_PRCFG2); 604 env->CSR_STLBPS = FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS, tlb_ps); 605 env->CSR_PWCL = FIELD_DP64(env->CSR_PWCL, CSR_PWCL, PTBASE, tlb_ps); 606 for (n = 0; n < 4; n++) { 607 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 608 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 609 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 610 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 611 } 612 613 #ifndef CONFIG_USER_ONLY 614 env->pc = 0x1c000000; 615 #ifdef CONFIG_TCG 616 memset(env->tlb, 0, sizeof(env->tlb)); 617 #endif 618 if (kvm_enabled()) { 619 kvm_arch_reset_vcpu(cs); 620 } 621 #endif 622 623 #ifdef CONFIG_TCG 624 restore_fp_status(env); 625 #endif 626 cs->exception_index = -1; 627 } 628 629 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 630 { 631 info->endian = BFD_ENDIAN_LITTLE; 632 info->print_insn = print_insn_loongarch; 633 } 634 635 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 636 { 637 CPUState *cs = CPU(dev); 638 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 639 Error *local_err = NULL; 640 641 cpu_exec_realizefn(cs, &local_err); 642 if (local_err != NULL) { 643 error_propagate(errp, local_err); 644 return; 645 } 646 647 loongarch_cpu_register_gdb_regs_for_features(cs); 648 649 qemu_init_vcpu(cs); 650 cpu_reset(cs); 651 652 lacc->parent_realize(dev, errp); 653 } 654 655 static void loongarch_cpu_unrealizefn(DeviceState *dev) 656 { 657 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 658 659 #ifndef CONFIG_USER_ONLY 660 cpu_remove_sync(CPU(dev)); 661 #endif 662 663 lacc->parent_unrealize(dev); 664 } 665 666 static bool loongarch_get_lsx(Object *obj, Error **errp) 667 { 668 return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF; 669 } 670 671 static void loongarch_set_lsx(Object *obj, bool value, Error **errp) 672 { 673 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 674 uint32_t val; 675 676 cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 677 if (cpu->lsx == ON_OFF_AUTO_OFF) { 678 cpu->lasx = ON_OFF_AUTO_OFF; 679 if (cpu->lasx == ON_OFF_AUTO_ON) { 680 error_setg(errp, "Failed to disable LSX since LASX is enabled"); 681 return; 682 } 683 } 684 685 if (kvm_enabled()) { 686 /* kvm feature detection in function kvm_arch_init_vcpu */ 687 return; 688 } 689 690 /* LSX feature detection in TCG mode */ 691 val = cpu->env.cpucfg[2]; 692 if (cpu->lsx == ON_OFF_AUTO_ON) { 693 if (FIELD_EX32(val, CPUCFG2, LSX) == 0) { 694 error_setg(errp, "Failed to enable LSX in TCG mode"); 695 return; 696 } 697 } else { 698 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0); 699 val = cpu->env.cpucfg[2]; 700 } 701 702 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value); 703 } 704 705 static bool loongarch_get_lasx(Object *obj, Error **errp) 706 { 707 return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF; 708 } 709 710 static void loongarch_set_lasx(Object *obj, bool value, Error **errp) 711 { 712 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 713 uint32_t val; 714 715 cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 716 if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) { 717 error_setg(errp, "Failed to enable LASX since lSX is disabled"); 718 return; 719 } 720 721 if (kvm_enabled()) { 722 /* kvm feature detection in function kvm_arch_init_vcpu */ 723 return; 724 } 725 726 /* LASX feature detection in TCG mode */ 727 val = cpu->env.cpucfg[2]; 728 if (cpu->lasx == ON_OFF_AUTO_ON) { 729 if (FIELD_EX32(val, CPUCFG2, LASX) == 0) { 730 error_setg(errp, "Failed to enable LASX in TCG mode"); 731 return; 732 } 733 } 734 735 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value); 736 } 737 738 void loongarch_cpu_post_init(Object *obj) 739 { 740 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 741 742 cpu->lbt = ON_OFF_AUTO_OFF; 743 cpu->pmu = ON_OFF_AUTO_OFF; 744 cpu->lsx = ON_OFF_AUTO_AUTO; 745 cpu->lasx = ON_OFF_AUTO_AUTO; 746 object_property_add_bool(obj, "lsx", loongarch_get_lsx, 747 loongarch_set_lsx); 748 object_property_add_bool(obj, "lasx", loongarch_get_lasx, 749 loongarch_set_lasx); 750 /* lbt is enabled only in kvm mode, not supported in tcg mode */ 751 if (kvm_enabled()) { 752 kvm_loongarch_cpu_post_init(cpu); 753 } 754 } 755 756 static void loongarch_cpu_init(Object *obj) 757 { 758 #ifndef CONFIG_USER_ONLY 759 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 760 761 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 762 #ifdef CONFIG_TCG 763 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 764 &loongarch_constant_timer_cb, cpu); 765 #endif 766 #endif 767 } 768 769 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 770 { 771 ObjectClass *oc; 772 773 oc = object_class_by_name(cpu_model); 774 if (!oc) { 775 g_autofree char *typename 776 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 777 oc = object_class_by_name(typename); 778 } 779 780 return oc; 781 } 782 783 static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f) 784 { 785 #ifndef CONFIG_USER_ONLY 786 CPULoongArchState *env = cpu_env(cs); 787 CSRInfo *csr_info; 788 int64_t *addr; 789 int i, j, len, col = 0; 790 791 qemu_fprintf(f, "\n"); 792 793 /* Dump all generic CSR register */ 794 for (i = 0; i < LOONGARCH_CSR_DBG; i++) { 795 csr_info = get_csr(i); 796 if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) { 797 if (i == (col + 3)) { 798 qemu_fprintf(f, "\n"); 799 } 800 801 continue; 802 } 803 804 if ((i > (col + 3)) || (i == col)) { 805 col = i & ~3; 806 qemu_fprintf(f, " CSR%03d:", col); 807 } 808 809 addr = (void *)env + csr_info->offset; 810 qemu_fprintf(f, " %s ", csr_info->name); 811 len = strlen(csr_info->name); 812 for (; len < 6; len++) { 813 qemu_fprintf(f, " "); 814 } 815 816 qemu_fprintf(f, "%" PRIx64, *addr); 817 j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1); 818 len += j / 4 + 1; 819 for (; len < 22; len++) { 820 qemu_fprintf(f, " "); 821 } 822 823 if (i == (col + 3)) { 824 qemu_fprintf(f, "\n"); 825 } 826 } 827 qemu_fprintf(f, "\n"); 828 #endif 829 } 830 831 static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 832 { 833 CPULoongArchState *env = cpu_env(cs); 834 int i; 835 836 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 837 qemu_fprintf(f, " FCSR0 0x%08x\n", env->fcsr0); 838 839 /* gpr */ 840 for (i = 0; i < 32; i++) { 841 if ((i & 3) == 0) { 842 qemu_fprintf(f, " GPR%02d:", i); 843 } 844 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 845 if ((i & 3) == 3) { 846 qemu_fprintf(f, "\n"); 847 } 848 } 849 850 /* csr */ 851 loongarch_cpu_dump_csr(cs, f); 852 853 /* fpr */ 854 if (flags & CPU_DUMP_FPU) { 855 for (i = 0; i < 32; i++) { 856 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i].vreg.D(0)); 857 if ((i & 3) == 3) { 858 qemu_fprintf(f, "\n"); 859 } 860 } 861 } 862 } 863 864 #ifdef CONFIG_TCG 865 #include "accel/tcg/cpu-ops.h" 866 867 static const TCGCPUOps loongarch_tcg_ops = { 868 .guest_default_memory_order = 0, 869 .mttcg_supported = true, 870 871 .initialize = loongarch_translate_init, 872 .translate_code = loongarch_translate_code, 873 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 874 .restore_state_to_opc = loongarch_restore_state_to_opc, 875 .mmu_index = loongarch_cpu_mmu_index, 876 877 #ifndef CONFIG_USER_ONLY 878 .tlb_fill = loongarch_cpu_tlb_fill, 879 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 880 .cpu_exec_halt = loongarch_cpu_has_work, 881 .do_interrupt = loongarch_cpu_do_interrupt, 882 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 883 #endif 884 }; 885 #endif /* CONFIG_TCG */ 886 887 #ifndef CONFIG_USER_ONLY 888 #include "hw/core/sysemu-cpu-ops.h" 889 890 static const struct SysemuCPUOps loongarch_sysemu_ops = { 891 .has_work = loongarch_cpu_has_work, 892 .write_elf64_note = loongarch_cpu_write_elf64_note, 893 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 894 }; 895 896 static int64_t loongarch_cpu_get_arch_id(CPUState *cs) 897 { 898 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 899 900 return cpu->phy_id; 901 } 902 #endif 903 904 static const Property loongarch_cpu_properties[] = { 905 DEFINE_PROP_INT32("socket-id", LoongArchCPU, socket_id, 0), 906 DEFINE_PROP_INT32("core-id", LoongArchCPU, core_id, 0), 907 DEFINE_PROP_INT32("thread-id", LoongArchCPU, thread_id, 0), 908 DEFINE_PROP_INT32("node-id", LoongArchCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 909 }; 910 911 static void loongarch_cpu_class_init(ObjectClass *c, const void *data) 912 { 913 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 914 CPUClass *cc = CPU_CLASS(c); 915 DeviceClass *dc = DEVICE_CLASS(c); 916 ResettableClass *rc = RESETTABLE_CLASS(c); 917 918 device_class_set_props(dc, loongarch_cpu_properties); 919 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 920 &lacc->parent_realize); 921 device_class_set_parent_unrealize(dc, loongarch_cpu_unrealizefn, 922 &lacc->parent_unrealize); 923 resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL, 924 &lacc->parent_phases); 925 926 cc->class_by_name = loongarch_cpu_class_by_name; 927 cc->dump_state = loongarch_cpu_dump_state; 928 cc->set_pc = loongarch_cpu_set_pc; 929 cc->get_pc = loongarch_cpu_get_pc; 930 #ifndef CONFIG_USER_ONLY 931 cc->get_arch_id = loongarch_cpu_get_arch_id; 932 dc->vmsd = &vmstate_loongarch_cpu; 933 cc->sysemu_ops = &loongarch_sysemu_ops; 934 #endif 935 cc->disas_set_info = loongarch_cpu_disas_set_info; 936 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 937 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 938 cc->gdb_stop_before_watchpoint = true; 939 940 #ifdef CONFIG_TCG 941 cc->tcg_ops = &loongarch_tcg_ops; 942 #endif 943 dc->user_creatable = true; 944 } 945 946 static const gchar *loongarch32_gdb_arch_name(CPUState *cs) 947 { 948 return "loongarch32"; 949 } 950 951 static void loongarch32_cpu_class_init(ObjectClass *c, const void *data) 952 { 953 CPUClass *cc = CPU_CLASS(c); 954 955 cc->gdb_core_xml_file = "loongarch-base32.xml"; 956 cc->gdb_arch_name = loongarch32_gdb_arch_name; 957 } 958 959 static const gchar *loongarch64_gdb_arch_name(CPUState *cs) 960 { 961 return "loongarch64"; 962 } 963 964 static void loongarch64_cpu_class_init(ObjectClass *c, const void *data) 965 { 966 CPUClass *cc = CPU_CLASS(c); 967 968 cc->gdb_core_xml_file = "loongarch-base64.xml"; 969 cc->gdb_arch_name = loongarch64_gdb_arch_name; 970 } 971 972 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ 973 { \ 974 .parent = TYPE_LOONGARCH##size##_CPU, \ 975 .instance_init = initfn, \ 976 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 977 } 978 979 static const TypeInfo loongarch_cpu_type_infos[] = { 980 { 981 .name = TYPE_LOONGARCH_CPU, 982 .parent = TYPE_CPU, 983 .instance_size = sizeof(LoongArchCPU), 984 .instance_align = __alignof(LoongArchCPU), 985 .instance_init = loongarch_cpu_init, 986 987 .abstract = true, 988 .class_size = sizeof(LoongArchCPUClass), 989 .class_init = loongarch_cpu_class_init, 990 }, 991 { 992 .name = TYPE_LOONGARCH32_CPU, 993 .parent = TYPE_LOONGARCH_CPU, 994 995 .abstract = true, 996 .class_init = loongarch32_cpu_class_init, 997 }, 998 { 999 .name = TYPE_LOONGARCH64_CPU, 1000 .parent = TYPE_LOONGARCH_CPU, 1001 1002 .abstract = true, 1003 .class_init = loongarch64_cpu_class_init, 1004 }, 1005 DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), 1006 DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), 1007 DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn), 1008 }; 1009 1010 DEFINE_TYPES(loongarch_cpu_type_infos) 1011