1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "system/qtest.h" 14 #include "system/tcg.h" 15 #include "system/kvm.h" 16 #include "kvm/kvm_loongarch.h" 17 #include "exec/exec-all.h" 18 #include "exec/translation-block.h" 19 #include "cpu.h" 20 #include "internals.h" 21 #include "fpu/softfloat-helpers.h" 22 #include "csr.h" 23 #ifndef CONFIG_USER_ONLY 24 #include "system/reset.h" 25 #endif 26 #include "vec.h" 27 #ifdef CONFIG_KVM 28 #include <linux/kvm.h> 29 #endif 30 #ifdef CONFIG_TCG 31 #include "exec/cpu_ldst.h" 32 #include "tcg/tcg.h" 33 #endif 34 35 const char * const regnames[32] = { 36 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 37 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 38 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 39 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 40 }; 41 42 const char * const fregnames[32] = { 43 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 44 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 45 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 46 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 47 }; 48 49 struct TypeExcp { 50 int32_t exccode; 51 const char * const name; 52 }; 53 54 static const struct TypeExcp excp_names[] = { 55 {EXCCODE_INT, "Interrupt"}, 56 {EXCCODE_PIL, "Page invalid exception for load"}, 57 {EXCCODE_PIS, "Page invalid exception for store"}, 58 {EXCCODE_PIF, "Page invalid exception for fetch"}, 59 {EXCCODE_PME, "Page modified exception"}, 60 {EXCCODE_PNR, "Page Not Readable exception"}, 61 {EXCCODE_PNX, "Page Not Executable exception"}, 62 {EXCCODE_PPI, "Page Privilege error"}, 63 {EXCCODE_ADEF, "Address error for instruction fetch"}, 64 {EXCCODE_ADEM, "Address error for Memory access"}, 65 {EXCCODE_SYS, "Syscall"}, 66 {EXCCODE_BRK, "Break"}, 67 {EXCCODE_INE, "Instruction Non-Existent"}, 68 {EXCCODE_IPE, "Instruction privilege error"}, 69 {EXCCODE_FPD, "Floating Point Disabled"}, 70 {EXCCODE_FPE, "Floating Point Exception"}, 71 {EXCCODE_DBP, "Debug breakpoint"}, 72 {EXCCODE_BCE, "Bound Check Exception"}, 73 {EXCCODE_SXD, "128 bit vector instructions Disable exception"}, 74 {EXCCODE_ASXD, "256 bit vector instructions Disable exception"}, 75 {EXCP_HLT, "EXCP_HLT"}, 76 }; 77 78 const char *loongarch_exception_name(int32_t exception) 79 { 80 int i; 81 82 for (i = 0; i < ARRAY_SIZE(excp_names); i++) { 83 if (excp_names[i].exccode == exception) { 84 return excp_names[i].name; 85 } 86 } 87 return "Unknown"; 88 } 89 90 void G_NORETURN do_raise_exception(CPULoongArchState *env, 91 uint32_t exception, 92 uintptr_t pc) 93 { 94 CPUState *cs = env_cpu(env); 95 96 qemu_log_mask(CPU_LOG_INT, "%s: exception: %d (%s)\n", 97 __func__, 98 exception, 99 loongarch_exception_name(exception)); 100 cs->exception_index = exception; 101 102 cpu_loop_exit_restore(cs, pc); 103 } 104 105 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 106 { 107 set_pc(cpu_env(cs), value); 108 } 109 110 static vaddr loongarch_cpu_get_pc(CPUState *cs) 111 { 112 return cpu_env(cs)->pc; 113 } 114 115 #ifndef CONFIG_USER_ONLY 116 #include "hw/loongarch/virt.h" 117 118 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 119 { 120 LoongArchCPU *cpu = opaque; 121 CPULoongArchState *env = &cpu->env; 122 CPUState *cs = CPU(cpu); 123 124 if (irq < 0 || irq >= N_IRQS) { 125 return; 126 } 127 128 if (kvm_enabled()) { 129 kvm_loongarch_set_interrupt(cpu, irq, level); 130 } else if (tcg_enabled()) { 131 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 132 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 133 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 134 } else { 135 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 136 } 137 } 138 } 139 140 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 141 { 142 bool ret = 0; 143 144 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 145 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 146 147 return ret; 148 } 149 150 /* Check if there is pending and not masked out interrupt */ 151 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 152 { 153 uint32_t pending; 154 uint32_t status; 155 156 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 157 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 158 159 return (pending & status) != 0; 160 } 161 #endif 162 163 #ifdef CONFIG_TCG 164 #ifndef CONFIG_USER_ONLY 165 static void loongarch_cpu_do_interrupt(CPUState *cs) 166 { 167 CPULoongArchState *env = cpu_env(cs); 168 bool update_badinstr = 1; 169 int cause = -1; 170 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 171 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 172 173 if (cs->exception_index != EXCCODE_INT) { 174 qemu_log_mask(CPU_LOG_INT, 175 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 176 " TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n", 177 __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA, 178 cs->exception_index, 179 loongarch_exception_name(cs->exception_index)); 180 } 181 182 switch (cs->exception_index) { 183 case EXCCODE_DBP: 184 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 185 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 186 goto set_DERA; 187 set_DERA: 188 env->CSR_DERA = env->pc; 189 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 190 set_pc(env, env->CSR_EENTRY + 0x480); 191 break; 192 case EXCCODE_INT: 193 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 194 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 195 goto set_DERA; 196 } 197 QEMU_FALLTHROUGH; 198 case EXCCODE_PIF: 199 case EXCCODE_ADEF: 200 cause = cs->exception_index; 201 update_badinstr = 0; 202 break; 203 case EXCCODE_SYS: 204 case EXCCODE_BRK: 205 case EXCCODE_INE: 206 case EXCCODE_IPE: 207 case EXCCODE_FPD: 208 case EXCCODE_FPE: 209 case EXCCODE_SXD: 210 case EXCCODE_ASXD: 211 env->CSR_BADV = env->pc; 212 QEMU_FALLTHROUGH; 213 case EXCCODE_BCE: 214 case EXCCODE_ADEM: 215 case EXCCODE_PIL: 216 case EXCCODE_PIS: 217 case EXCCODE_PME: 218 case EXCCODE_PNR: 219 case EXCCODE_PNX: 220 case EXCCODE_PPI: 221 cause = cs->exception_index; 222 break; 223 default: 224 qemu_log("Error: exception(%d) has not been supported\n", 225 cs->exception_index); 226 abort(); 227 } 228 229 if (update_badinstr) { 230 env->CSR_BADI = cpu_ldl_code(env, env->pc); 231 } 232 233 /* Save PLV and IE */ 234 if (tlbfill) { 235 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 236 FIELD_EX64(env->CSR_CRMD, 237 CSR_CRMD, PLV)); 238 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 239 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 240 /* set the DA mode */ 241 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 242 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 243 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 244 PC, (env->pc >> 2)); 245 } else { 246 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, 247 EXCODE_MCODE(cause)); 248 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, 249 EXCODE_SUBCODE(cause)); 250 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 251 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 252 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 253 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 254 env->CSR_ERA = env->pc; 255 } 256 257 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 258 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 259 260 if (vec_size) { 261 vec_size = (1 << vec_size) * 4; 262 } 263 264 if (cs->exception_index == EXCCODE_INT) { 265 /* Interrupt */ 266 uint32_t vector = 0; 267 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 268 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 269 270 /* Find the highest-priority interrupt. */ 271 vector = 31 - clz32(pending); 272 set_pc(env, env->CSR_EENTRY + \ 273 (EXCCODE_EXTERNAL_INT + vector) * vec_size); 274 qemu_log_mask(CPU_LOG_INT, 275 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 276 " cause %d\n" " A " TARGET_FMT_lx " D " 277 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 278 TARGET_FMT_lx "\n", 279 __func__, env->pc, env->CSR_ERA, 280 cause, env->CSR_BADV, env->CSR_DERA, vector, 281 env->CSR_ECFG, env->CSR_ESTAT); 282 } else { 283 if (tlbfill) { 284 set_pc(env, env->CSR_TLBRENTRY); 285 } else { 286 set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); 287 } 288 qemu_log_mask(CPU_LOG_INT, 289 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 290 " cause %d%s\n, ESTAT " TARGET_FMT_lx 291 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 292 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 293 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 294 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 295 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 296 env->CSR_ECFG, 297 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 298 env->CSR_BADI, env->gpr[11], cs->cpu_index, 299 env->CSR_ASID); 300 } 301 cs->exception_index = -1; 302 } 303 304 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 305 vaddr addr, unsigned size, 306 MMUAccessType access_type, 307 int mmu_idx, MemTxAttrs attrs, 308 MemTxResult response, 309 uintptr_t retaddr) 310 { 311 CPULoongArchState *env = cpu_env(cs); 312 313 if (access_type == MMU_INST_FETCH) { 314 do_raise_exception(env, EXCCODE_ADEF, retaddr); 315 } else { 316 do_raise_exception(env, EXCCODE_ADEM, retaddr); 317 } 318 } 319 320 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 321 { 322 if (interrupt_request & CPU_INTERRUPT_HARD) { 323 CPULoongArchState *env = cpu_env(cs); 324 325 if (cpu_loongarch_hw_interrupts_enabled(env) && 326 cpu_loongarch_hw_interrupts_pending(env)) { 327 /* Raise it */ 328 cs->exception_index = EXCCODE_INT; 329 loongarch_cpu_do_interrupt(cs); 330 return true; 331 } 332 } 333 return false; 334 } 335 #endif 336 337 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 338 const TranslationBlock *tb) 339 { 340 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 341 set_pc(cpu_env(cs), tb->pc); 342 } 343 344 static void loongarch_restore_state_to_opc(CPUState *cs, 345 const TranslationBlock *tb, 346 const uint64_t *data) 347 { 348 set_pc(cpu_env(cs), data[0]); 349 } 350 #endif /* CONFIG_TCG */ 351 352 static bool loongarch_cpu_has_work(CPUState *cs) 353 { 354 #ifdef CONFIG_USER_ONLY 355 return true; 356 #else 357 bool has_work = false; 358 359 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 360 cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) { 361 has_work = true; 362 } 363 364 return has_work; 365 #endif 366 } 367 368 static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) 369 { 370 CPULoongArchState *env = cpu_env(cs); 371 372 if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { 373 return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); 374 } 375 return MMU_DA_IDX; 376 } 377 378 static void loongarch_la464_init_csr(Object *obj) 379 { 380 #ifndef CONFIG_USER_ONLY 381 static bool initialized; 382 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 383 CPULoongArchState *env = &cpu->env; 384 int i, num; 385 386 if (!initialized) { 387 initialized = true; 388 num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM); 389 for (i = num; i < 16; i++) { 390 set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED); 391 } 392 set_csr_flag(LOONGARCH_CSR_IMPCTL1, CSRFL_UNUSED); 393 set_csr_flag(LOONGARCH_CSR_IMPCTL2, CSRFL_UNUSED); 394 set_csr_flag(LOONGARCH_CSR_MERRCTL, CSRFL_UNUSED); 395 set_csr_flag(LOONGARCH_CSR_MERRINFO1, CSRFL_UNUSED); 396 set_csr_flag(LOONGARCH_CSR_MERRINFO2, CSRFL_UNUSED); 397 set_csr_flag(LOONGARCH_CSR_MERRENTRY, CSRFL_UNUSED); 398 set_csr_flag(LOONGARCH_CSR_MERRERA, CSRFL_UNUSED); 399 set_csr_flag(LOONGARCH_CSR_MERRSAVE, CSRFL_UNUSED); 400 set_csr_flag(LOONGARCH_CSR_CTAG, CSRFL_UNUSED); 401 } 402 #endif 403 } 404 405 static void loongarch_la464_initfn(Object *obj) 406 { 407 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 408 CPULoongArchState *env = &cpu->env; 409 uint32_t data = 0, field; 410 int i; 411 412 for (i = 0; i < 21; i++) { 413 env->cpucfg[i] = 0x0; 414 } 415 416 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; 417 env->cpucfg[0] = 0x14c010; /* PRID */ 418 419 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 420 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 421 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 422 if (kvm_enabled()) { 423 /* GPA address width of VM is 47, field value is 47 - 1 */ 424 field = 0x2e; 425 } else { 426 field = 0x2f; /* 48 bit - 1 */ 427 } 428 data = FIELD_DP32(data, CPUCFG1, PALEN, field); 429 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 430 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 431 data = FIELD_DP32(data, CPUCFG1, RI, 1); 432 data = FIELD_DP32(data, CPUCFG1, EP, 1); 433 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 434 data = FIELD_DP32(data, CPUCFG1, HP, 1); 435 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 436 env->cpucfg[1] = data; 437 438 data = 0; 439 data = FIELD_DP32(data, CPUCFG2, FP, 1); 440 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 441 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 442 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 443 data = FIELD_DP32(data, CPUCFG2, LSX, 1), 444 data = FIELD_DP32(data, CPUCFG2, LASX, 1), 445 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 446 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 447 data = FIELD_DP32(data, CPUCFG2, LSPW, 1); 448 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 449 env->cpucfg[2] = data; 450 451 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 452 453 data = 0; 454 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 455 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 456 env->cpucfg[5] = data; 457 458 data = 0; 459 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 460 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 461 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 462 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 463 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 464 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 465 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 466 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 467 env->cpucfg[16] = data; 468 469 data = 0; 470 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 471 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 472 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 473 env->cpucfg[17] = data; 474 475 data = 0; 476 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 477 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 478 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 479 env->cpucfg[18] = data; 480 481 data = 0; 482 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 483 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 484 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 485 env->cpucfg[19] = data; 486 487 data = 0; 488 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 489 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 490 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); 491 env->cpucfg[20] = data; 492 493 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 494 495 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, 8); 496 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS, 0x2f); 497 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 7); 498 499 env->CSR_PRCFG2 = 0x3ffff000; 500 501 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 502 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 503 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 504 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 505 506 loongarch_la464_init_csr(obj); 507 loongarch_cpu_post_init(obj); 508 } 509 510 static void loongarch_la132_initfn(Object *obj) 511 { 512 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 513 CPULoongArchState *env = &cpu->env; 514 uint32_t data = 0; 515 int i; 516 517 for (i = 0; i < 21; i++) { 518 env->cpucfg[i] = 0x0; 519 } 520 521 cpu->dtb_compatible = "loongarch,Loongson-1C103"; 522 env->cpucfg[0] = 0x148042; /* PRID */ 523 524 data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ 525 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 526 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 527 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ 528 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ 529 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 530 data = FIELD_DP32(data, CPUCFG1, RI, 0); 531 data = FIELD_DP32(data, CPUCFG1, EP, 0); 532 data = FIELD_DP32(data, CPUCFG1, RPLV, 0); 533 data = FIELD_DP32(data, CPUCFG1, HP, 1); 534 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 535 env->cpucfg[1] = data; 536 } 537 538 static void loongarch_max_initfn(Object *obj) 539 { 540 /* '-cpu max' for TCG: we use cpu la464. */ 541 loongarch_la464_initfn(obj); 542 } 543 544 static void loongarch_cpu_reset_hold(Object *obj, ResetType type) 545 { 546 CPUState *cs = CPU(obj); 547 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(obj); 548 CPULoongArchState *env = cpu_env(cs); 549 550 if (lacc->parent_phases.hold) { 551 lacc->parent_phases.hold(obj, type); 552 } 553 554 #ifdef CONFIG_TCG 555 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 556 #endif 557 env->fcsr0 = 0x0; 558 559 int n; 560 /* Set csr registers value after reset, see the manual 6.4. */ 561 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 562 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 563 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 564 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 565 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 0); 566 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 0); 567 568 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 569 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 570 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 571 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 572 573 env->CSR_MISC = 0; 574 575 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 576 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 577 578 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 579 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 580 env->CSR_CPUID = cs->cpu_index; 581 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 582 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 583 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 584 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 585 env->CSR_TID = cs->cpu_index; 586 /* 587 * Workaround for edk2-stable202408, CSR PGD register is set only if 588 * its value is equal to zero for boot cpu, it causes reboot issue. 589 * 590 * Here clear CSR registers relative with TLB. 591 */ 592 env->CSR_PGDH = 0; 593 env->CSR_PGDL = 0; 594 env->CSR_PWCL = 0; 595 env->CSR_PWCH = 0; 596 env->CSR_STLBPS = 0; 597 env->CSR_EENTRY = 0; 598 env->CSR_TLBRENTRY = 0; 599 env->CSR_MERRENTRY = 0; 600 601 for (n = 0; n < 4; n++) { 602 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 603 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 604 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 605 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 606 } 607 608 #ifndef CONFIG_USER_ONLY 609 env->pc = 0x1c000000; 610 #ifdef CONFIG_TCG 611 memset(env->tlb, 0, sizeof(env->tlb)); 612 #endif 613 if (kvm_enabled()) { 614 kvm_arch_reset_vcpu(cs); 615 } 616 #endif 617 618 #ifdef CONFIG_TCG 619 restore_fp_status(env); 620 #endif 621 cs->exception_index = -1; 622 } 623 624 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 625 { 626 info->print_insn = print_insn_loongarch; 627 } 628 629 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 630 { 631 CPUState *cs = CPU(dev); 632 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 633 Error *local_err = NULL; 634 635 cpu_exec_realizefn(cs, &local_err); 636 if (local_err != NULL) { 637 error_propagate(errp, local_err); 638 return; 639 } 640 641 loongarch_cpu_register_gdb_regs_for_features(cs); 642 643 cpu_reset(cs); 644 qemu_init_vcpu(cs); 645 646 lacc->parent_realize(dev, errp); 647 } 648 649 static bool loongarch_get_lsx(Object *obj, Error **errp) 650 { 651 return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF; 652 } 653 654 static void loongarch_set_lsx(Object *obj, bool value, Error **errp) 655 { 656 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 657 uint32_t val; 658 659 cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 660 if (cpu->lsx == ON_OFF_AUTO_OFF) { 661 cpu->lasx = ON_OFF_AUTO_OFF; 662 if (cpu->lasx == ON_OFF_AUTO_ON) { 663 error_setg(errp, "Failed to disable LSX since LASX is enabled"); 664 return; 665 } 666 } 667 668 if (kvm_enabled()) { 669 /* kvm feature detection in function kvm_arch_init_vcpu */ 670 return; 671 } 672 673 /* LSX feature detection in TCG mode */ 674 val = cpu->env.cpucfg[2]; 675 if (cpu->lsx == ON_OFF_AUTO_ON) { 676 if (FIELD_EX32(val, CPUCFG2, LSX) == 0) { 677 error_setg(errp, "Failed to enable LSX in TCG mode"); 678 return; 679 } 680 } else { 681 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0); 682 val = cpu->env.cpucfg[2]; 683 } 684 685 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value); 686 } 687 688 static bool loongarch_get_lasx(Object *obj, Error **errp) 689 { 690 return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF; 691 } 692 693 static void loongarch_set_lasx(Object *obj, bool value, Error **errp) 694 { 695 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 696 uint32_t val; 697 698 cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 699 if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) { 700 error_setg(errp, "Failed to enable LASX since lSX is disabled"); 701 return; 702 } 703 704 if (kvm_enabled()) { 705 /* kvm feature detection in function kvm_arch_init_vcpu */ 706 return; 707 } 708 709 /* LASX feature detection in TCG mode */ 710 val = cpu->env.cpucfg[2]; 711 if (cpu->lasx == ON_OFF_AUTO_ON) { 712 if (FIELD_EX32(val, CPUCFG2, LASX) == 0) { 713 error_setg(errp, "Failed to enable LASX in TCG mode"); 714 return; 715 } 716 } 717 718 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value); 719 } 720 721 void loongarch_cpu_post_init(Object *obj) 722 { 723 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 724 725 cpu->lbt = ON_OFF_AUTO_OFF; 726 cpu->pmu = ON_OFF_AUTO_OFF; 727 cpu->lsx = ON_OFF_AUTO_AUTO; 728 cpu->lasx = ON_OFF_AUTO_AUTO; 729 object_property_add_bool(obj, "lsx", loongarch_get_lsx, 730 loongarch_set_lsx); 731 object_property_add_bool(obj, "lasx", loongarch_get_lasx, 732 loongarch_set_lasx); 733 /* lbt is enabled only in kvm mode, not supported in tcg mode */ 734 if (kvm_enabled()) { 735 kvm_loongarch_cpu_post_init(cpu); 736 } 737 } 738 739 static void loongarch_cpu_init(Object *obj) 740 { 741 #ifndef CONFIG_USER_ONLY 742 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 743 744 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 745 #ifdef CONFIG_TCG 746 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 747 &loongarch_constant_timer_cb, cpu); 748 #endif 749 #endif 750 } 751 752 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 753 { 754 ObjectClass *oc; 755 756 oc = object_class_by_name(cpu_model); 757 if (!oc) { 758 g_autofree char *typename 759 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 760 oc = object_class_by_name(typename); 761 } 762 763 return oc; 764 } 765 766 static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f) 767 { 768 #ifndef CONFIG_USER_ONLY 769 CPULoongArchState *env = cpu_env(cs); 770 CSRInfo *csr_info; 771 int64_t *addr; 772 int i, j, len, col = 0; 773 774 qemu_fprintf(f, "\n"); 775 776 /* Dump all generic CSR register */ 777 for (i = 0; i < LOONGARCH_CSR_DBG; i++) { 778 csr_info = get_csr(i); 779 if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) { 780 if (i == (col + 3)) { 781 qemu_fprintf(f, "\n"); 782 } 783 784 continue; 785 } 786 787 if ((i > (col + 3)) || (i == col)) { 788 col = i & ~3; 789 qemu_fprintf(f, " CSR%03d:", col); 790 } 791 792 addr = (void *)env + csr_info->offset; 793 qemu_fprintf(f, " %s ", csr_info->name); 794 len = strlen(csr_info->name); 795 for (; len < 6; len++) { 796 qemu_fprintf(f, " "); 797 } 798 799 qemu_fprintf(f, "%" PRIx64, *addr); 800 j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1); 801 len += j / 4 + 1; 802 for (; len < 22; len++) { 803 qemu_fprintf(f, " "); 804 } 805 806 if (i == (col + 3)) { 807 qemu_fprintf(f, "\n"); 808 } 809 } 810 qemu_fprintf(f, "\n"); 811 #endif 812 } 813 814 static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 815 { 816 CPULoongArchState *env = cpu_env(cs); 817 int i; 818 819 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 820 qemu_fprintf(f, " FCSR0 0x%08x\n", env->fcsr0); 821 822 /* gpr */ 823 for (i = 0; i < 32; i++) { 824 if ((i & 3) == 0) { 825 qemu_fprintf(f, " GPR%02d:", i); 826 } 827 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 828 if ((i & 3) == 3) { 829 qemu_fprintf(f, "\n"); 830 } 831 } 832 833 /* csr */ 834 loongarch_cpu_dump_csr(cs, f); 835 836 /* fpr */ 837 if (flags & CPU_DUMP_FPU) { 838 for (i = 0; i < 32; i++) { 839 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i].vreg.D(0)); 840 if ((i & 3) == 3) { 841 qemu_fprintf(f, "\n"); 842 } 843 } 844 } 845 } 846 847 #ifdef CONFIG_TCG 848 #include "hw/core/tcg-cpu-ops.h" 849 850 static const TCGCPUOps loongarch_tcg_ops = { 851 .initialize = loongarch_translate_init, 852 .translate_code = loongarch_translate_code, 853 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 854 .restore_state_to_opc = loongarch_restore_state_to_opc, 855 856 #ifndef CONFIG_USER_ONLY 857 .tlb_fill = loongarch_cpu_tlb_fill, 858 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 859 .cpu_exec_halt = loongarch_cpu_has_work, 860 .do_interrupt = loongarch_cpu_do_interrupt, 861 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 862 #endif 863 }; 864 #endif /* CONFIG_TCG */ 865 866 #ifndef CONFIG_USER_ONLY 867 #include "hw/core/sysemu-cpu-ops.h" 868 869 static const struct SysemuCPUOps loongarch_sysemu_ops = { 870 .write_elf64_note = loongarch_cpu_write_elf64_note, 871 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 872 }; 873 874 static int64_t loongarch_cpu_get_arch_id(CPUState *cs) 875 { 876 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 877 878 return cpu->phy_id; 879 } 880 #endif 881 882 static void loongarch_cpu_class_init(ObjectClass *c, void *data) 883 { 884 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 885 CPUClass *cc = CPU_CLASS(c); 886 DeviceClass *dc = DEVICE_CLASS(c); 887 ResettableClass *rc = RESETTABLE_CLASS(c); 888 889 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 890 &lacc->parent_realize); 891 resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL, 892 &lacc->parent_phases); 893 894 cc->class_by_name = loongarch_cpu_class_by_name; 895 cc->has_work = loongarch_cpu_has_work; 896 cc->mmu_index = loongarch_cpu_mmu_index; 897 cc->dump_state = loongarch_cpu_dump_state; 898 cc->set_pc = loongarch_cpu_set_pc; 899 cc->get_pc = loongarch_cpu_get_pc; 900 #ifndef CONFIG_USER_ONLY 901 cc->get_arch_id = loongarch_cpu_get_arch_id; 902 dc->vmsd = &vmstate_loongarch_cpu; 903 cc->sysemu_ops = &loongarch_sysemu_ops; 904 #endif 905 cc->disas_set_info = loongarch_cpu_disas_set_info; 906 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 907 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 908 cc->gdb_stop_before_watchpoint = true; 909 910 #ifdef CONFIG_TCG 911 cc->tcg_ops = &loongarch_tcg_ops; 912 #endif 913 } 914 915 static const gchar *loongarch32_gdb_arch_name(CPUState *cs) 916 { 917 return "loongarch32"; 918 } 919 920 static void loongarch32_cpu_class_init(ObjectClass *c, void *data) 921 { 922 CPUClass *cc = CPU_CLASS(c); 923 924 cc->gdb_core_xml_file = "loongarch-base32.xml"; 925 cc->gdb_arch_name = loongarch32_gdb_arch_name; 926 } 927 928 static const gchar *loongarch64_gdb_arch_name(CPUState *cs) 929 { 930 return "loongarch64"; 931 } 932 933 static void loongarch64_cpu_class_init(ObjectClass *c, void *data) 934 { 935 CPUClass *cc = CPU_CLASS(c); 936 937 cc->gdb_core_xml_file = "loongarch-base64.xml"; 938 cc->gdb_arch_name = loongarch64_gdb_arch_name; 939 } 940 941 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ 942 { \ 943 .parent = TYPE_LOONGARCH##size##_CPU, \ 944 .instance_init = initfn, \ 945 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 946 } 947 948 static const TypeInfo loongarch_cpu_type_infos[] = { 949 { 950 .name = TYPE_LOONGARCH_CPU, 951 .parent = TYPE_CPU, 952 .instance_size = sizeof(LoongArchCPU), 953 .instance_align = __alignof(LoongArchCPU), 954 .instance_init = loongarch_cpu_init, 955 956 .abstract = true, 957 .class_size = sizeof(LoongArchCPUClass), 958 .class_init = loongarch_cpu_class_init, 959 }, 960 { 961 .name = TYPE_LOONGARCH32_CPU, 962 .parent = TYPE_LOONGARCH_CPU, 963 964 .abstract = true, 965 .class_init = loongarch32_cpu_class_init, 966 }, 967 { 968 .name = TYPE_LOONGARCH64_CPU, 969 .parent = TYPE_LOONGARCH_CPU, 970 971 .abstract = true, 972 .class_init = loongarch64_cpu_class_init, 973 }, 974 DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), 975 DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), 976 DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn), 977 }; 978 979 DEFINE_TYPES(loongarch_cpu_type_infos) 980