xref: /qemu/target/i386/tcg/user/excp_helper.c (revision 7cef6d686309e2792186504ae17cf4f3eb57ef68)
1 /*
2  *  x86 exception helpers - user-mode specific code
3  *
4  *  Copyright (c) 2003 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "tcg/helper-tcg.h"
23 
x86_cpu_record_sigsegv(CPUState * cs,vaddr addr,MMUAccessType access_type,bool maperr,uintptr_t ra)24 void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr,
25                             MMUAccessType access_type,
26                             bool maperr, uintptr_t ra)
27 {
28     X86CPU *cpu = X86_CPU(cs);
29     CPUX86State *env = &cpu->env;
30 
31     /*
32      * The error_code that hw reports as part of the exception frame
33      * is copied to linux sigcontext.err.  The exception_index is
34      * copied to linux sigcontext.trapno.  Short of inventing a new
35      * place to store the trapno, we cannot let our caller raise the
36      * signal and set exception_index to EXCP_INTERRUPT.
37      */
38     env->cr[2] = addr;
39     env->error_code = ((access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT)
40                     | (maperr ? 0 : PG_ERROR_P_MASK)
41                     | PG_ERROR_U_MASK;
42     cs->exception_index = EXCP0E_PAGE;
43 
44     /* Disable do_interrupt_user. */
45     env->exception_is_int = 0;
46     env->exception_next_eip = -1;
47 
48     cpu_loop_exit_restore(cs, ra);
49 }
50 
x86_cpu_record_sigbus(CPUState * cs,vaddr addr,MMUAccessType access_type,uintptr_t ra)51 void x86_cpu_record_sigbus(CPUState *cs, vaddr addr,
52                            MMUAccessType access_type, uintptr_t ra)
53 {
54     X86CPU *cpu = X86_CPU(cs);
55     handle_unaligned_access(&cpu->env, addr, access_type, ra);
56 }
57