1 /*
2 * x86 exception helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "qemu/log.h"
23 #include "system/runstate.h"
24 #include "exec/helper-proto.h"
25 #include "helper-tcg.h"
26
helper_raise_interrupt(CPUX86State * env,int intno,int next_eip_addend)27 G_NORETURN void helper_raise_interrupt(CPUX86State *env, int intno,
28 int next_eip_addend)
29 {
30 raise_interrupt(env, intno, next_eip_addend);
31 }
32
helper_raise_exception(CPUX86State * env,int exception_index)33 G_NORETURN void helper_raise_exception(CPUX86State *env, int exception_index)
34 {
35 raise_exception(env, exception_index);
36 }
37
38 /*
39 * Check nested exceptions and change to double or triple fault if
40 * needed. It should only be called, if this is not an interrupt.
41 * Returns the new exception number.
42 */
check_exception(CPUX86State * env,int intno,int * error_code,uintptr_t retaddr)43 static int check_exception(CPUX86State *env, int intno, int *error_code,
44 uintptr_t retaddr)
45 {
46 int first_contributory = env->old_exception == 0 ||
47 (env->old_exception >= 10 &&
48 env->old_exception <= 13);
49 int second_contributory = intno == 0 ||
50 (intno >= 10 && intno <= 13);
51
52 qemu_log_mask(CPU_LOG_INT, "check_exception old: 0x%x new 0x%x\n",
53 env->old_exception, intno);
54
55 #if !defined(CONFIG_USER_ONLY)
56 if (env->old_exception == EXCP08_DBLE) {
57 if (env->hflags & HF_GUEST_MASK) {
58 cpu_vmexit(env, SVM_EXIT_SHUTDOWN, 0, retaddr); /* does not return */
59 }
60
61 qemu_log_mask(CPU_LOG_RESET, "Triple fault\n");
62
63 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
64 return EXCP_HLT;
65 }
66 #endif
67
68 if ((first_contributory && second_contributory)
69 || (env->old_exception == EXCP0E_PAGE &&
70 (second_contributory || (intno == EXCP0E_PAGE)))) {
71 intno = EXCP08_DBLE;
72 *error_code = 0;
73 }
74
75 if (second_contributory || (intno == EXCP0E_PAGE) ||
76 (intno == EXCP08_DBLE)) {
77 env->old_exception = intno;
78 }
79
80 return intno;
81 }
82
83 /*
84 * Signal an interruption. It is executed in the main CPU loop.
85 * is_int is TRUE if coming from the int instruction. next_eip is the
86 * env->eip value AFTER the interrupt instruction. It is only relevant if
87 * is_int is TRUE.
88 */
89 static G_NORETURN
raise_interrupt2(CPUX86State * env,int intno,int is_int,int error_code,int next_eip_addend,uintptr_t retaddr)90 void raise_interrupt2(CPUX86State *env, int intno,
91 int is_int, int error_code,
92 int next_eip_addend,
93 uintptr_t retaddr)
94 {
95 CPUState *cs = env_cpu(env);
96
97 if (!is_int) {
98 cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno,
99 error_code, retaddr);
100 intno = check_exception(env, intno, &error_code, retaddr);
101 } else {
102 cpu_svm_check_intercept_param(env, SVM_EXIT_SWINT, 0, retaddr);
103 }
104
105 cs->exception_index = intno;
106 env->error_code = error_code;
107 env->exception_is_int = is_int;
108 env->exception_next_eip = env->eip + next_eip_addend;
109 cpu_loop_exit_restore(cs, retaddr);
110 }
111
112 /* shortcuts to generate exceptions */
113
raise_interrupt(CPUX86State * env,int intno,int next_eip_addend)114 G_NORETURN void raise_interrupt(CPUX86State *env, int intno, int next_eip_addend)
115 {
116 raise_interrupt2(env, intno, 1, 0, next_eip_addend, 0);
117 }
118
raise_exception_err(CPUX86State * env,int exception_index,int error_code)119 G_NORETURN void raise_exception_err(CPUX86State *env, int exception_index,
120 int error_code)
121 {
122 raise_interrupt2(env, exception_index, 0, error_code, 0, 0);
123 }
124
raise_exception_err_ra(CPUX86State * env,int exception_index,int error_code,uintptr_t retaddr)125 G_NORETURN void raise_exception_err_ra(CPUX86State *env, int exception_index,
126 int error_code, uintptr_t retaddr)
127 {
128 raise_interrupt2(env, exception_index, 0, error_code, 0, retaddr);
129 }
130
raise_exception(CPUX86State * env,int exception_index)131 G_NORETURN void raise_exception(CPUX86State *env, int exception_index)
132 {
133 raise_interrupt2(env, exception_index, 0, 0, 0, 0);
134 }
135
raise_exception_ra(CPUX86State * env,int exception_index,uintptr_t retaddr)136 G_NORETURN void raise_exception_ra(CPUX86State *env, int exception_index,
137 uintptr_t retaddr)
138 {
139 raise_interrupt2(env, exception_index, 0, 0, 0, retaddr);
140 }
141
helper_icebp(CPUX86State * env)142 G_NORETURN void helper_icebp(CPUX86State *env)
143 {
144 CPUState *cs = env_cpu(env);
145
146 do_end_instruction(env);
147
148 /*
149 * INT1 aka ICEBP generates a trap-like #DB, but it is pretty special.
150 *
151 * "Although the ICEBP instruction dispatches through IDT vector 1,
152 * that event is not interceptable by means of the #DB exception
153 * intercept". Instead there is a separate fault-like ICEBP intercept.
154 */
155 cs->exception_index = EXCP01_DB;
156 env->error_code = 0;
157 env->exception_is_int = 0;
158 env->exception_next_eip = env->eip;
159 cpu_loop_exit(cs);
160 }
161
handle_unaligned_access(CPUX86State * env,vaddr vaddr,MMUAccessType access_type,uintptr_t retaddr)162 G_NORETURN void handle_unaligned_access(CPUX86State *env, vaddr vaddr,
163 MMUAccessType access_type,
164 uintptr_t retaddr)
165 {
166 /*
167 * Unaligned accesses are currently only triggered by SSE/AVX
168 * instructions that impose alignment requirements on memory
169 * operands. These instructions raise #GP(0) upon accessing an
170 * unaligned address.
171 */
172 raise_exception_ra(env, EXCP0D_GPF, retaddr);
173 }
174