1 /*
2 * Helpers for HPPA FPU instructions.
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "fpu/softfloat.h"
24
HELPER(loaded_fr0)25 void HELPER(loaded_fr0)(CPUHPPAState *env)
26 {
27 uint32_t shadow = env->fr[0] >> 32;
28 int rm, d;
29
30 env->fr0_shadow = shadow;
31
32 switch (FIELD_EX32(shadow, FPSR, RM)) {
33 default:
34 rm = float_round_nearest_even;
35 break;
36 case 1:
37 rm = float_round_to_zero;
38 break;
39 case 2:
40 rm = float_round_up;
41 break;
42 case 3:
43 rm = float_round_down;
44 break;
45 }
46 set_float_rounding_mode(rm, &env->fp_status);
47
48 d = FIELD_EX32(shadow, FPSR, D);
49 set_flush_to_zero(d, &env->fp_status);
50 set_flush_inputs_to_zero(d, &env->fp_status);
51
52 /*
53 * TODO: we only need to do this at CPU reset, but currently
54 * HPPA does note implement a CPU reset method at all...
55 */
56 set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
57 /*
58 * TODO: The HPPA architecture reference only documents its NaN
59 * propagation rule for 2-operand operations. Testing on real hardware
60 * might be necessary to confirm whether this order for muladd is correct.
61 * Not preferring the SNaN is almost certainly incorrect as it diverges
62 * from the documented rules for 2-operand operations.
63 */
64 set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
65 /* For inf * 0 + NaN, return the input NaN */
66 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
67 /* Default NaN: sign bit clear, msb-1 frac bit set */
68 set_float_default_nan_pattern(0b00100000, &env->fp_status);
69 set_snan_bit_is_one(true, &env->fp_status);
70 /*
71 * "PA-RISC 2.0 Architecture" says it is IMPDEF whether the flushing
72 * enabled by FPSR.D happens before or after rounding. We pick "before"
73 * for consistency with tininess detection.
74 */
75 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status);
76 /*
77 * TODO: "PA-RISC 2.0 Architecture" chapter 10 says that we should
78 * detect tininess before rounding, but we don't set that here so we
79 * get the default tininess after rounding.
80 */
81 }
82
cpu_hppa_loaded_fr0(CPUHPPAState * env)83 void cpu_hppa_loaded_fr0(CPUHPPAState *env)
84 {
85 helper_loaded_fr0(env);
86 }
87
88 #define CONVERT_BIT(X, SRC, DST) \
89 ((unsigned)(SRC) > (unsigned)(DST) \
90 ? (X) / ((SRC) / (DST)) & (DST) \
91 : ((X) & (SRC)) * ((DST) / (SRC)))
92
update_fr0_op(CPUHPPAState * env,uintptr_t ra)93 static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
94 {
95 uint32_t soft_exp = get_float_exception_flags(&env->fp_status);
96 uint32_t hard_exp = 0;
97 uint32_t shadow = env->fr0_shadow & 0x3ffffff;
98 uint32_t fr1 = 0;
99
100 if (likely(soft_exp == 0)) {
101 env->fr[0] = (uint64_t)shadow << 32;
102 return;
103 }
104 set_float_exception_flags(0, &env->fp_status);
105
106 hard_exp |= CONVERT_BIT(soft_exp, float_flag_inexact, R_FPSR_ENA_I_MASK);
107 hard_exp |= CONVERT_BIT(soft_exp, float_flag_underflow, R_FPSR_ENA_U_MASK);
108 hard_exp |= CONVERT_BIT(soft_exp, float_flag_overflow, R_FPSR_ENA_O_MASK);
109 hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, R_FPSR_ENA_Z_MASK);
110 hard_exp |= CONVERT_BIT(soft_exp, float_flag_invalid, R_FPSR_ENA_V_MASK);
111 if (hard_exp & shadow) {
112 shadow = FIELD_DP32(shadow, FPSR, T, 1);
113 /* fill exception register #1, which is lower 32-bits of fr[0] */
114 #if !defined(CONFIG_USER_ONLY)
115 if (hard_exp & (R_FPSR_ENA_O_MASK | R_FPSR_ENA_U_MASK)) {
116 /* over- and underflow both set overflow flag only */
117 fr1 = FIELD_DP32(fr1, FPSR, C, 1);
118 fr1 = FIELD_DP32(fr1, FPSR, FLG_O, 1);
119 } else
120 #endif
121 {
122 fr1 |= hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT);
123 }
124 }
125 env->fr0_shadow = shadow;
126 env->fr[0] = (uint64_t)shadow << 32 | fr1;
127
128 if (hard_exp & shadow) {
129 hppa_dynamic_excp(env, EXCP_ASSIST, ra);
130 }
131 }
132
HELPER(fsqrt_s)133 float32 HELPER(fsqrt_s)(CPUHPPAState *env, float32 arg)
134 {
135 float32 ret = float32_sqrt(arg, &env->fp_status);
136 update_fr0_op(env, GETPC());
137 return ret;
138 }
139
HELPER(frnd_s)140 float32 HELPER(frnd_s)(CPUHPPAState *env, float32 arg)
141 {
142 float32 ret = float32_round_to_int(arg, &env->fp_status);
143 update_fr0_op(env, GETPC());
144 return ret;
145 }
146
HELPER(fadd_s)147 float32 HELPER(fadd_s)(CPUHPPAState *env, float32 a, float32 b)
148 {
149 float32 ret = float32_add(a, b, &env->fp_status);
150 update_fr0_op(env, GETPC());
151 return ret;
152 }
153
HELPER(fsub_s)154 float32 HELPER(fsub_s)(CPUHPPAState *env, float32 a, float32 b)
155 {
156 float32 ret = float32_sub(a, b, &env->fp_status);
157 update_fr0_op(env, GETPC());
158 return ret;
159 }
160
HELPER(fmpy_s)161 float32 HELPER(fmpy_s)(CPUHPPAState *env, float32 a, float32 b)
162 {
163 float32 ret = float32_mul(a, b, &env->fp_status);
164 update_fr0_op(env, GETPC());
165 return ret;
166 }
167
HELPER(fdiv_s)168 float32 HELPER(fdiv_s)(CPUHPPAState *env, float32 a, float32 b)
169 {
170 float32 ret = float32_div(a, b, &env->fp_status);
171 update_fr0_op(env, GETPC());
172 return ret;
173 }
174
HELPER(fsqrt_d)175 float64 HELPER(fsqrt_d)(CPUHPPAState *env, float64 arg)
176 {
177 float64 ret = float64_sqrt(arg, &env->fp_status);
178 update_fr0_op(env, GETPC());
179 return ret;
180 }
181
HELPER(frnd_d)182 float64 HELPER(frnd_d)(CPUHPPAState *env, float64 arg)
183 {
184 float64 ret = float64_round_to_int(arg, &env->fp_status);
185 update_fr0_op(env, GETPC());
186 return ret;
187 }
188
HELPER(fadd_d)189 float64 HELPER(fadd_d)(CPUHPPAState *env, float64 a, float64 b)
190 {
191 float64 ret = float64_add(a, b, &env->fp_status);
192 update_fr0_op(env, GETPC());
193 return ret;
194 }
195
HELPER(fsub_d)196 float64 HELPER(fsub_d)(CPUHPPAState *env, float64 a, float64 b)
197 {
198 float64 ret = float64_sub(a, b, &env->fp_status);
199 update_fr0_op(env, GETPC());
200 return ret;
201 }
202
HELPER(fmpy_d)203 float64 HELPER(fmpy_d)(CPUHPPAState *env, float64 a, float64 b)
204 {
205 float64 ret = float64_mul(a, b, &env->fp_status);
206 update_fr0_op(env, GETPC());
207 return ret;
208 }
209
HELPER(fdiv_d)210 float64 HELPER(fdiv_d)(CPUHPPAState *env, float64 a, float64 b)
211 {
212 float64 ret = float64_div(a, b, &env->fp_status);
213 update_fr0_op(env, GETPC());
214 return ret;
215 }
216
HELPER(fcnv_s_d)217 float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg)
218 {
219 float64 ret = float32_to_float64(arg, &env->fp_status);
220 update_fr0_op(env, GETPC());
221 return ret;
222 }
223
HELPER(fcnv_d_s)224 float32 HELPER(fcnv_d_s)(CPUHPPAState *env, float64 arg)
225 {
226 float32 ret = float64_to_float32(arg, &env->fp_status);
227 update_fr0_op(env, GETPC());
228 return ret;
229 }
230
HELPER(fcnv_w_s)231 float32 HELPER(fcnv_w_s)(CPUHPPAState *env, int32_t arg)
232 {
233 float32 ret = int32_to_float32(arg, &env->fp_status);
234 update_fr0_op(env, GETPC());
235 return ret;
236 }
237
HELPER(fcnv_dw_s)238 float32 HELPER(fcnv_dw_s)(CPUHPPAState *env, int64_t arg)
239 {
240 float32 ret = int64_to_float32(arg, &env->fp_status);
241 update_fr0_op(env, GETPC());
242 return ret;
243 }
244
HELPER(fcnv_w_d)245 float64 HELPER(fcnv_w_d)(CPUHPPAState *env, int32_t arg)
246 {
247 float64 ret = int32_to_float64(arg, &env->fp_status);
248 update_fr0_op(env, GETPC());
249 return ret;
250 }
251
HELPER(fcnv_dw_d)252 float64 HELPER(fcnv_dw_d)(CPUHPPAState *env, int64_t arg)
253 {
254 float64 ret = int64_to_float64(arg, &env->fp_status);
255 update_fr0_op(env, GETPC());
256 return ret;
257 }
258
HELPER(fcnv_s_w)259 int32_t HELPER(fcnv_s_w)(CPUHPPAState *env, float32 arg)
260 {
261 int32_t ret = float32_to_int32(arg, &env->fp_status);
262 update_fr0_op(env, GETPC());
263 return ret;
264 }
265
HELPER(fcnv_d_w)266 int32_t HELPER(fcnv_d_w)(CPUHPPAState *env, float64 arg)
267 {
268 int32_t ret = float64_to_int32(arg, &env->fp_status);
269 update_fr0_op(env, GETPC());
270 return ret;
271 }
272
HELPER(fcnv_s_dw)273 int64_t HELPER(fcnv_s_dw)(CPUHPPAState *env, float32 arg)
274 {
275 int64_t ret = float32_to_int64(arg, &env->fp_status);
276 update_fr0_op(env, GETPC());
277 return ret;
278 }
279
HELPER(fcnv_d_dw)280 int64_t HELPER(fcnv_d_dw)(CPUHPPAState *env, float64 arg)
281 {
282 int64_t ret = float64_to_int64(arg, &env->fp_status);
283 update_fr0_op(env, GETPC());
284 return ret;
285 }
286
HELPER(fcnv_t_s_w)287 int32_t HELPER(fcnv_t_s_w)(CPUHPPAState *env, float32 arg)
288 {
289 int32_t ret = float32_to_int32_round_to_zero(arg, &env->fp_status);
290 update_fr0_op(env, GETPC());
291 return ret;
292 }
293
HELPER(fcnv_t_d_w)294 int32_t HELPER(fcnv_t_d_w)(CPUHPPAState *env, float64 arg)
295 {
296 int32_t ret = float64_to_int32_round_to_zero(arg, &env->fp_status);
297 update_fr0_op(env, GETPC());
298 return ret;
299 }
300
HELPER(fcnv_t_s_dw)301 int64_t HELPER(fcnv_t_s_dw)(CPUHPPAState *env, float32 arg)
302 {
303 int64_t ret = float32_to_int64_round_to_zero(arg, &env->fp_status);
304 update_fr0_op(env, GETPC());
305 return ret;
306 }
307
HELPER(fcnv_t_d_dw)308 int64_t HELPER(fcnv_t_d_dw)(CPUHPPAState *env, float64 arg)
309 {
310 int64_t ret = float64_to_int64_round_to_zero(arg, &env->fp_status);
311 update_fr0_op(env, GETPC());
312 return ret;
313 }
314
HELPER(fcnv_uw_s)315 float32 HELPER(fcnv_uw_s)(CPUHPPAState *env, uint32_t arg)
316 {
317 float32 ret = uint32_to_float32(arg, &env->fp_status);
318 update_fr0_op(env, GETPC());
319 return ret;
320 }
321
HELPER(fcnv_udw_s)322 float32 HELPER(fcnv_udw_s)(CPUHPPAState *env, uint64_t arg)
323 {
324 float32 ret = uint64_to_float32(arg, &env->fp_status);
325 update_fr0_op(env, GETPC());
326 return ret;
327 }
328
HELPER(fcnv_uw_d)329 float64 HELPER(fcnv_uw_d)(CPUHPPAState *env, uint32_t arg)
330 {
331 float64 ret = uint32_to_float64(arg, &env->fp_status);
332 update_fr0_op(env, GETPC());
333 return ret;
334 }
335
HELPER(fcnv_udw_d)336 float64 HELPER(fcnv_udw_d)(CPUHPPAState *env, uint64_t arg)
337 {
338 float64 ret = uint64_to_float64(arg, &env->fp_status);
339 update_fr0_op(env, GETPC());
340 return ret;
341 }
342
HELPER(fcnv_s_uw)343 uint32_t HELPER(fcnv_s_uw)(CPUHPPAState *env, float32 arg)
344 {
345 uint32_t ret = float32_to_uint32(arg, &env->fp_status);
346 update_fr0_op(env, GETPC());
347 return ret;
348 }
349
HELPER(fcnv_d_uw)350 uint32_t HELPER(fcnv_d_uw)(CPUHPPAState *env, float64 arg)
351 {
352 uint32_t ret = float64_to_uint32(arg, &env->fp_status);
353 update_fr0_op(env, GETPC());
354 return ret;
355 }
356
HELPER(fcnv_s_udw)357 uint64_t HELPER(fcnv_s_udw)(CPUHPPAState *env, float32 arg)
358 {
359 uint64_t ret = float32_to_uint64(arg, &env->fp_status);
360 update_fr0_op(env, GETPC());
361 return ret;
362 }
363
HELPER(fcnv_d_udw)364 uint64_t HELPER(fcnv_d_udw)(CPUHPPAState *env, float64 arg)
365 {
366 uint64_t ret = float64_to_uint64(arg, &env->fp_status);
367 update_fr0_op(env, GETPC());
368 return ret;
369 }
370
HELPER(fcnv_t_s_uw)371 uint32_t HELPER(fcnv_t_s_uw)(CPUHPPAState *env, float32 arg)
372 {
373 uint32_t ret = float32_to_uint32_round_to_zero(arg, &env->fp_status);
374 update_fr0_op(env, GETPC());
375 return ret;
376 }
377
HELPER(fcnv_t_d_uw)378 uint32_t HELPER(fcnv_t_d_uw)(CPUHPPAState *env, float64 arg)
379 {
380 uint32_t ret = float64_to_uint32_round_to_zero(arg, &env->fp_status);
381 update_fr0_op(env, GETPC());
382 return ret;
383 }
384
HELPER(fcnv_t_s_udw)385 uint64_t HELPER(fcnv_t_s_udw)(CPUHPPAState *env, float32 arg)
386 {
387 uint64_t ret = float32_to_uint64_round_to_zero(arg, &env->fp_status);
388 update_fr0_op(env, GETPC());
389 return ret;
390 }
391
HELPER(fcnv_t_d_udw)392 uint64_t HELPER(fcnv_t_d_udw)(CPUHPPAState *env, float64 arg)
393 {
394 uint64_t ret = float64_to_uint64_round_to_zero(arg, &env->fp_status);
395 update_fr0_op(env, GETPC());
396 return ret;
397 }
398
update_fr0_cmp(CPUHPPAState * env,uint32_t y,uint32_t c,FloatRelation r)399 static void update_fr0_cmp(CPUHPPAState *env, uint32_t y,
400 uint32_t c, FloatRelation r)
401 {
402 uint32_t shadow = env->fr0_shadow;
403
404 switch (r) {
405 case float_relation_greater:
406 c = extract32(c, 4, 1);
407 break;
408 case float_relation_less:
409 c = extract32(c, 3, 1);
410 break;
411 case float_relation_equal:
412 c = extract32(c, 2, 1);
413 break;
414 case float_relation_unordered:
415 c = extract32(c, 1, 1);
416 break;
417 default:
418 g_assert_not_reached();
419 }
420
421 if (y) {
422 /* targeted comparison */
423 /* set fpsr[ca[y - 1]] to current compare */
424 shadow = deposit32(shadow, R_FPSR_CA0_SHIFT - (y - 1), 1, c);
425 } else {
426 /* queued comparison */
427 /* shift cq right by one place */
428 shadow = (shadow & ~R_FPSR_CQ_MASK) | ((shadow >> 1) & R_FPSR_CQ_MASK);
429 /* move fpsr[c] to fpsr[cq[0]] */
430 shadow = FIELD_DP32(shadow, FPSR, CQ0, FIELD_EX32(shadow, FPSR, C));
431 /* set fpsr[c] to current compare */
432 shadow = FIELD_DP32(shadow, FPSR, C, c);
433 }
434
435 env->fr0_shadow = shadow;
436 env->fr[0] = (uint64_t)shadow << 32;
437 }
438
HELPER(fcmp_s)439 void HELPER(fcmp_s)(CPUHPPAState *env, float32 a, float32 b,
440 uint32_t y, uint32_t c)
441 {
442 FloatRelation r;
443 if (c & 1) {
444 r = float32_compare(a, b, &env->fp_status);
445 } else {
446 r = float32_compare_quiet(a, b, &env->fp_status);
447 }
448 update_fr0_op(env, GETPC());
449 update_fr0_cmp(env, y, c, r);
450 }
451
HELPER(fcmp_d)452 void HELPER(fcmp_d)(CPUHPPAState *env, float64 a, float64 b,
453 uint32_t y, uint32_t c)
454 {
455 FloatRelation r;
456 if (c & 1) {
457 r = float64_compare(a, b, &env->fp_status);
458 } else {
459 r = float64_compare_quiet(a, b, &env->fp_status);
460 }
461 update_fr0_op(env, GETPC());
462 update_fr0_cmp(env, y, c, r);
463 }
464
HELPER(fmpyfadd_s)465 float32 HELPER(fmpyfadd_s)(CPUHPPAState *env, float32 a, float32 b, float32 c)
466 {
467 float32 ret = float32_muladd(a, b, c, 0, &env->fp_status);
468 update_fr0_op(env, GETPC());
469 return ret;
470 }
471
HELPER(fmpynfadd_s)472 float32 HELPER(fmpynfadd_s)(CPUHPPAState *env, float32 a, float32 b, float32 c)
473 {
474 float32 ret = float32_muladd(a, b, c, float_muladd_negate_product,
475 &env->fp_status);
476 update_fr0_op(env, GETPC());
477 return ret;
478 }
479
HELPER(fmpyfadd_d)480 float64 HELPER(fmpyfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c)
481 {
482 float64 ret = float64_muladd(a, b, c, 0, &env->fp_status);
483 update_fr0_op(env, GETPC());
484 return ret;
485 }
486
HELPER(fmpynfadd_d)487 float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c)
488 {
489 float64 ret = float64_muladd(a, b, c, float_muladd_negate_product,
490 &env->fp_status);
491 update_fr0_op(env, GETPC());
492 return ret;
493 }
494