1 /* 2 * Copyright (C) 2014 - Linaro 3 * Author: Rob Herring <rob.herring@linaro.org> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 #include "qemu/osdep.h" 19 #include "cpu.h" 20 #include "exec/helper-proto.h" 21 #include "kvm-consts.h" 22 #include "sysemu/sysemu.h" 23 #include "internals.h" 24 #include "arm-powerctl.h" 25 #include "exec/exec-all.h" 26 27 bool arm_is_psci_call(ARMCPU *cpu, int excp_type) 28 { 29 /* Return true if the r0/x0 value indicates a PSCI call and 30 * the exception type matches the configured PSCI conduit. This is 31 * called before the SMC/HVC instruction is executed, to decide whether 32 * we should treat it as a PSCI call or with the architecturally 33 * defined behaviour for an SMC or HVC (which might be UNDEF or trap 34 * to EL2 or to EL3). 35 */ 36 CPUARMState *env = &cpu->env; 37 uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0]; 38 39 switch (excp_type) { 40 case EXCP_HVC: 41 if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_HVC) { 42 return false; 43 } 44 break; 45 case EXCP_SMC: 46 if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { 47 return false; 48 } 49 break; 50 default: 51 return false; 52 } 53 54 switch (param) { 55 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 56 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 57 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 58 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 59 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 60 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 61 case QEMU_PSCI_0_1_FN_CPU_ON: 62 case QEMU_PSCI_0_2_FN_CPU_ON: 63 case QEMU_PSCI_0_2_FN64_CPU_ON: 64 case QEMU_PSCI_0_1_FN_CPU_OFF: 65 case QEMU_PSCI_0_2_FN_CPU_OFF: 66 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 67 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 68 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 69 case QEMU_PSCI_0_1_FN_MIGRATE: 70 case QEMU_PSCI_0_2_FN_MIGRATE: 71 return true; 72 default: 73 return false; 74 } 75 } 76 77 void arm_handle_psci_call(ARMCPU *cpu) 78 { 79 /* 80 * This function partially implements the logic for dispatching Power State 81 * Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b), 82 * to the extent required for bringing up and taking down secondary cores, 83 * and for handling reset and poweroff requests. 84 * Additional information about the calling convention used is available in 85 * the document 'SMC Calling Convention' (ARM DEN 0028) 86 */ 87 CPUARMState *env = &cpu->env; 88 uint64_t param[4]; 89 uint64_t context_id, mpidr; 90 target_ulong entry; 91 int32_t ret = 0; 92 int i; 93 94 for (i = 0; i < 4; i++) { 95 /* 96 * All PSCI functions take explicit 32-bit or native int sized 97 * arguments so we can simply zero-extend all arguments regardless 98 * of which exact function we are about to call. 99 */ 100 param[i] = is_a64(env) ? env->xregs[i] : env->regs[i]; 101 } 102 103 if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) { 104 ret = QEMU_PSCI_RET_INVALID_PARAMS; 105 goto err; 106 } 107 108 switch (param[0]) { 109 CPUState *target_cpu_state; 110 ARMCPU *target_cpu; 111 112 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 113 ret = QEMU_PSCI_0_2_RET_VERSION_0_2; 114 break; 115 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 116 ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ 117 break; 118 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 119 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 120 mpidr = param[1]; 121 122 switch (param[2]) { 123 case 0: 124 target_cpu_state = arm_get_cpu_by_id(mpidr); 125 if (!target_cpu_state) { 126 ret = QEMU_PSCI_RET_INVALID_PARAMS; 127 break; 128 } 129 target_cpu = ARM_CPU(target_cpu_state); 130 ret = target_cpu->powered_off ? 1 : 0; 131 break; 132 default: 133 /* Everything above affinity level 0 is always on. */ 134 ret = 0; 135 } 136 break; 137 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 138 qemu_system_reset_request(); 139 /* QEMU reset and shutdown are async requests, but PSCI 140 * mandates that we never return from the reset/shutdown 141 * call, so power the CPU off now so it doesn't execute 142 * anything further. 143 */ 144 goto cpu_off; 145 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 146 qemu_system_shutdown_request(); 147 goto cpu_off; 148 case QEMU_PSCI_0_1_FN_CPU_ON: 149 case QEMU_PSCI_0_2_FN_CPU_ON: 150 case QEMU_PSCI_0_2_FN64_CPU_ON: 151 mpidr = param[1]; 152 entry = param[2]; 153 context_id = param[3]; 154 /* 155 * The PSCI spec mandates that newly brought up CPUs enter the 156 * exception level of the caller in the same execution mode as 157 * the caller, with context_id in x0/r0, respectively. 158 */ 159 ret = arm_set_cpu_on(mpidr, entry, context_id, arm_current_el(env), 160 is_a64(env)); 161 break; 162 case QEMU_PSCI_0_1_FN_CPU_OFF: 163 case QEMU_PSCI_0_2_FN_CPU_OFF: 164 goto cpu_off; 165 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 166 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 167 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 168 /* Affinity levels are not supported in QEMU */ 169 if (param[1] & 0xfffe0000) { 170 ret = QEMU_PSCI_RET_INVALID_PARAMS; 171 break; 172 } 173 /* Powerdown is not supported, we always go into WFI */ 174 if (is_a64(env)) { 175 env->xregs[0] = 0; 176 } else { 177 env->regs[0] = 0; 178 } 179 helper_wfi(env); 180 break; 181 case QEMU_PSCI_0_1_FN_MIGRATE: 182 case QEMU_PSCI_0_2_FN_MIGRATE: 183 ret = QEMU_PSCI_RET_NOT_SUPPORTED; 184 break; 185 default: 186 g_assert_not_reached(); 187 } 188 189 err: 190 if (is_a64(env)) { 191 env->xregs[0] = ret; 192 } else { 193 env->regs[0] = ret; 194 } 195 return; 196 197 cpu_off: 198 ret = arm_set_cpu_off(cpu->mp_affinity); 199 /* notreached */ 200 /* sanity check in case something failed */ 201 assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); 202 } 203