1 // Copyright 2024, Linaro Limited 2 // Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org> 3 // SPDX-License-Identifier: GPL-2.0-or-later 4 5 use core::ptr::{addr_of_mut, NonNull}; 6 use std::{ 7 ffi::CStr, 8 os::raw::{c_int, c_uchar, c_uint, c_void}, 9 }; 10 11 use qemu_api::{ 12 bindings::{self, *}, 13 c_str, 14 definitions::ObjectImpl, 15 device_class::DeviceImpl, 16 impl_device_class, 17 irq::InterruptSource, 18 prelude::*, 19 }; 20 21 use crate::{ 22 device_class, 23 memory_ops::PL011_OPS, 24 registers::{self, Interrupt}, 25 RegisterOffset, 26 }; 27 28 /// Integer Baud Rate Divider, `UARTIBRD` 29 const IBRD_MASK: u32 = 0xffff; 30 31 /// Fractional Baud Rate Divider, `UARTFBRD` 32 const FBRD_MASK: u32 = 0x3f; 33 34 const DATA_BREAK: u32 = 1 << 10; 35 36 /// QEMU sourced constant. 37 pub const PL011_FIFO_DEPTH: usize = 16_usize; 38 39 #[derive(Clone, Copy, Debug)] 40 enum DeviceId { 41 #[allow(dead_code)] 42 Arm = 0, 43 Luminary, 44 } 45 46 impl std::ops::Index<hwaddr> for DeviceId { 47 type Output = c_uchar; 48 49 fn index(&self, idx: hwaddr) -> &Self::Output { 50 match self { 51 Self::Arm => &Self::PL011_ID_ARM[idx as usize], 52 Self::Luminary => &Self::PL011_ID_LUMINARY[idx as usize], 53 } 54 } 55 } 56 57 impl DeviceId { 58 const PL011_ID_ARM: [c_uchar; 8] = [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1]; 59 const PL011_ID_LUMINARY: [c_uchar; 8] = [0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1]; 60 } 61 62 #[repr(C)] 63 #[derive(Debug, qemu_api_macros::Object, qemu_api_macros::offsets)] 64 /// PL011 Device Model in QEMU 65 pub struct PL011State { 66 pub parent_obj: SysBusDevice, 67 pub iomem: MemoryRegion, 68 #[doc(alias = "fr")] 69 pub flags: registers::Flags, 70 #[doc(alias = "lcr")] 71 pub line_control: registers::LineControl, 72 #[doc(alias = "rsr")] 73 pub receive_status_error_clear: registers::ReceiveStatusErrorClear, 74 #[doc(alias = "cr")] 75 pub control: registers::Control, 76 pub dmacr: u32, 77 pub int_enabled: u32, 78 pub int_level: u32, 79 pub read_fifo: [u32; PL011_FIFO_DEPTH], 80 pub ilpr: u32, 81 pub ibrd: u32, 82 pub fbrd: u32, 83 pub ifl: u32, 84 pub read_pos: usize, 85 pub read_count: usize, 86 pub read_trigger: usize, 87 #[doc(alias = "chr")] 88 pub char_backend: CharBackend, 89 /// QEMU interrupts 90 /// 91 /// ```text 92 /// * sysbus MMIO region 0: device registers 93 /// * sysbus IRQ 0: `UARTINTR` (combined interrupt line) 94 /// * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line) 95 /// * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line) 96 /// * sysbus IRQ 3: `UARTRTINTR` (receive timeout interrupt line) 97 /// * sysbus IRQ 4: `UARTMSINTR` (momem status interrupt line) 98 /// * sysbus IRQ 5: `UARTEINTR` (error interrupt line) 99 /// ``` 100 #[doc(alias = "irq")] 101 pub interrupts: [InterruptSource; IRQMASK.len()], 102 #[doc(alias = "clk")] 103 pub clock: NonNull<Clock>, 104 #[doc(alias = "migrate_clk")] 105 pub migrate_clock: bool, 106 /// The byte string that identifies the device. 107 device_id: DeviceId, 108 } 109 110 unsafe impl ObjectType for PL011State { 111 type Class = PL011Class; 112 const TYPE_NAME: &'static CStr = crate::TYPE_PL011; 113 } 114 115 impl ObjectImpl for PL011State { 116 type ParentType = SysBusDevice; 117 118 const INSTANCE_INIT: Option<unsafe fn(&mut Self)> = Some(Self::init); 119 } 120 121 #[repr(C)] 122 pub struct PL011Class { 123 _inner: [u8; 0], 124 } 125 126 impl DeviceImpl for PL011State { 127 fn properties() -> &'static [Property] { 128 &device_class::PL011_PROPERTIES 129 } 130 fn vmsd() -> Option<&'static VMStateDescription> { 131 Some(&device_class::VMSTATE_PL011) 132 } 133 const REALIZE: Option<fn(&mut Self)> = Some(Self::realize); 134 const RESET: Option<fn(&mut Self)> = Some(Self::reset); 135 } 136 137 impl_device_class!(PL011State); 138 139 impl PL011State { 140 /// Initializes a pre-allocated, unitialized instance of `PL011State`. 141 /// 142 /// # Safety 143 /// 144 /// `self` must point to a correctly sized and aligned location for the 145 /// `PL011State` type. It must not be called more than once on the same 146 /// location/instance. All its fields are expected to hold unitialized 147 /// values with the sole exception of `parent_obj`. 148 unsafe fn init(&mut self) { 149 const CLK_NAME: &CStr = c_str!("clk"); 150 151 let sbd = unsafe { &mut *(addr_of_mut!(*self).cast::<SysBusDevice>()) }; 152 153 // SAFETY: 154 // 155 // self and self.iomem are guaranteed to be valid at this point since callers 156 // must make sure the `self` reference is valid. 157 unsafe { 158 memory_region_init_io( 159 addr_of_mut!(self.iomem), 160 addr_of_mut!(*self).cast::<Object>(), 161 &PL011_OPS, 162 addr_of_mut!(*self).cast::<c_void>(), 163 Self::TYPE_NAME.as_ptr(), 164 0x1000, 165 ); 166 sysbus_init_mmio(sbd, addr_of_mut!(self.iomem)); 167 } 168 169 for irq in self.interrupts.iter() { 170 sbd.init_irq(irq); 171 } 172 173 let dev = addr_of_mut!(*self).cast::<DeviceState>(); 174 175 // SAFETY: 176 // 177 // self.clock is not initialized at this point; but since `NonNull<_>` is Copy, 178 // we can overwrite the undefined value without side effects. This is 179 // safe since all PL011State instances are created by QOM code which 180 // calls this function to initialize the fields; therefore no code is 181 // able to access an invalid self.clock value. 182 unsafe { 183 self.clock = NonNull::new(qdev_init_clock_in( 184 dev, 185 CLK_NAME.as_ptr(), 186 None, /* pl011_clock_update */ 187 addr_of_mut!(*self).cast::<c_void>(), 188 ClockEvent::ClockUpdate.0, 189 )) 190 .unwrap(); 191 } 192 } 193 194 pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::ControlFlow<u64, u64> { 195 use RegisterOffset::*; 196 197 std::ops::ControlFlow::Break(match RegisterOffset::try_from(offset) { 198 Err(v) if (0x3f8..0x400).contains(&(v >> 2)) => { 199 u64::from(self.device_id[(offset - 0xfe0) >> 2]) 200 } 201 Err(_) => { 202 // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset 0x%x\n", (int)offset); 203 0 204 } 205 Ok(DR) => { 206 self.flags.set_receive_fifo_full(false); 207 let c = self.read_fifo[self.read_pos]; 208 if self.read_count > 0 { 209 self.read_count -= 1; 210 self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1); 211 } 212 if self.read_count == 0 { 213 self.flags.set_receive_fifo_empty(true); 214 } 215 if self.read_count + 1 == self.read_trigger { 216 self.int_level &= !registers::INT_RX; 217 } 218 // Update error bits. 219 self.receive_status_error_clear = c.to_be_bytes()[3].into(); 220 self.update(); 221 // Must call qemu_chr_fe_accept_input, so return Continue: 222 return std::ops::ControlFlow::Continue(c.into()); 223 } 224 Ok(RSR) => u8::from(self.receive_status_error_clear).into(), 225 Ok(FR) => u16::from(self.flags).into(), 226 Ok(FBRD) => self.fbrd.into(), 227 Ok(ILPR) => self.ilpr.into(), 228 Ok(IBRD) => self.ibrd.into(), 229 Ok(LCR_H) => u16::from(self.line_control).into(), 230 Ok(CR) => { 231 // We exercise our self-control. 232 u16::from(self.control).into() 233 } 234 Ok(FLS) => self.ifl.into(), 235 Ok(IMSC) => self.int_enabled.into(), 236 Ok(RIS) => self.int_level.into(), 237 Ok(MIS) => u64::from(self.int_level & self.int_enabled), 238 Ok(ICR) => { 239 // "The UARTICR Register is the interrupt clear register and is write-only" 240 // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, UARTICR 241 0 242 } 243 Ok(DMACR) => self.dmacr.into(), 244 }) 245 } 246 247 pub fn write(&mut self, offset: hwaddr, value: u64) { 248 // eprintln!("write offset {offset} value {value}"); 249 use RegisterOffset::*; 250 let value: u32 = value as u32; 251 match RegisterOffset::try_from(offset) { 252 Err(_bad_offset) => { 253 eprintln!("write bad offset {offset} value {value}"); 254 } 255 Ok(DR) => { 256 // ??? Check if transmitter is enabled. 257 let ch: u8 = value as u8; 258 // XXX this blocks entire thread. Rewrite to use 259 // qemu_chr_fe_write and background I/O callbacks 260 261 // SAFETY: self.char_backend is a valid CharBackend instance after it's been 262 // initialized in realize(). 263 unsafe { 264 qemu_chr_fe_write_all(addr_of_mut!(self.char_backend), &ch, 1); 265 } 266 self.loopback_tx(value); 267 self.int_level |= registers::INT_TX; 268 self.update(); 269 } 270 Ok(RSR) => { 271 self.receive_status_error_clear = 0.into(); 272 } 273 Ok(FR) => { 274 // flag writes are ignored 275 } 276 Ok(ILPR) => { 277 self.ilpr = value; 278 } 279 Ok(IBRD) => { 280 self.ibrd = value; 281 } 282 Ok(FBRD) => { 283 self.fbrd = value; 284 } 285 Ok(LCR_H) => { 286 let value = value as u16; 287 let new_val: registers::LineControl = value.into(); 288 // Reset the FIFO state on FIFO enable or disable 289 if bool::from(self.line_control.fifos_enabled()) 290 ^ bool::from(new_val.fifos_enabled()) 291 { 292 self.reset_fifo(); 293 } 294 if self.line_control.send_break() ^ new_val.send_break() { 295 let mut break_enable: c_int = new_val.send_break().into(); 296 // SAFETY: self.char_backend is a valid CharBackend instance after it's been 297 // initialized in realize(). 298 unsafe { 299 qemu_chr_fe_ioctl( 300 addr_of_mut!(self.char_backend), 301 CHR_IOCTL_SERIAL_SET_BREAK as i32, 302 addr_of_mut!(break_enable).cast::<c_void>(), 303 ); 304 } 305 self.loopback_break(break_enable > 0); 306 } 307 self.line_control = new_val; 308 self.set_read_trigger(); 309 } 310 Ok(CR) => { 311 // ??? Need to implement the enable bit. 312 let value = value as u16; 313 self.control = value.into(); 314 self.loopback_mdmctrl(); 315 } 316 Ok(FLS) => { 317 self.ifl = value; 318 self.set_read_trigger(); 319 } 320 Ok(IMSC) => { 321 self.int_enabled = value; 322 self.update(); 323 } 324 Ok(RIS) => {} 325 Ok(MIS) => {} 326 Ok(ICR) => { 327 self.int_level &= !value; 328 self.update(); 329 } 330 Ok(DMACR) => { 331 self.dmacr = value; 332 if value & 3 > 0 { 333 // qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n"); 334 eprintln!("pl011: DMA not implemented"); 335 } 336 } 337 } 338 } 339 340 #[inline] 341 fn loopback_tx(&mut self, value: u32) { 342 if !self.loopback_enabled() { 343 return; 344 } 345 346 // Caveat: 347 // 348 // In real hardware, TX loopback happens at the serial-bit level 349 // and then reassembled by the RX logics back into bytes and placed 350 // into the RX fifo. That is, loopback happens after TX fifo. 351 // 352 // Because the real hardware TX fifo is time-drained at the frame 353 // rate governed by the configured serial format, some loopback 354 // bytes in TX fifo may still be able to get into the RX fifo 355 // that could be full at times while being drained at software 356 // pace. 357 // 358 // In such scenario, the RX draining pace is the major factor 359 // deciding which loopback bytes get into the RX fifo, unless 360 // hardware flow-control is enabled. 361 // 362 // For simplicity, the above described is not emulated. 363 self.put_fifo(value); 364 } 365 366 fn loopback_mdmctrl(&mut self) { 367 if !self.loopback_enabled() { 368 return; 369 } 370 371 /* 372 * Loopback software-driven modem control outputs to modem status inputs: 373 * FR.RI <= CR.Out2 374 * FR.DCD <= CR.Out1 375 * FR.CTS <= CR.RTS 376 * FR.DSR <= CR.DTR 377 * 378 * The loopback happens immediately even if this call is triggered 379 * by setting only CR.LBE. 380 * 381 * CTS/RTS updates due to enabled hardware flow controls are not 382 * dealt with here. 383 */ 384 385 self.flags.set_ring_indicator(self.control.out_2()); 386 self.flags.set_data_carrier_detect(self.control.out_1()); 387 self.flags.set_clear_to_send(self.control.request_to_send()); 388 self.flags 389 .set_data_set_ready(self.control.data_transmit_ready()); 390 391 // Change interrupts based on updated FR 392 let mut il = self.int_level; 393 394 il &= !Interrupt::MS; 395 396 if self.flags.data_set_ready() { 397 il |= Interrupt::DSR as u32; 398 } 399 if self.flags.data_carrier_detect() { 400 il |= Interrupt::DCD as u32; 401 } 402 if self.flags.clear_to_send() { 403 il |= Interrupt::CTS as u32; 404 } 405 if self.flags.ring_indicator() { 406 il |= Interrupt::RI as u32; 407 } 408 self.int_level = il; 409 self.update(); 410 } 411 412 fn loopback_break(&mut self, enable: bool) { 413 if enable { 414 self.loopback_tx(DATA_BREAK); 415 } 416 } 417 418 fn set_read_trigger(&mut self) { 419 self.read_trigger = 1; 420 } 421 422 pub fn realize(&mut self) { 423 // SAFETY: self.char_backend has the correct size and alignment for a 424 // CharBackend object, and its callbacks are of the correct types. 425 unsafe { 426 qemu_chr_fe_set_handlers( 427 addr_of_mut!(self.char_backend), 428 Some(pl011_can_receive), 429 Some(pl011_receive), 430 Some(pl011_event), 431 None, 432 addr_of_mut!(*self).cast::<c_void>(), 433 core::ptr::null_mut(), 434 true, 435 ); 436 } 437 } 438 439 pub fn reset(&mut self) { 440 self.line_control.reset(); 441 self.receive_status_error_clear.reset(); 442 self.dmacr = 0; 443 self.int_enabled = 0; 444 self.int_level = 0; 445 self.ilpr = 0; 446 self.ibrd = 0; 447 self.fbrd = 0; 448 self.read_trigger = 1; 449 self.ifl = 0x12; 450 self.control.reset(); 451 self.flags = 0.into(); 452 self.reset_fifo(); 453 } 454 455 pub fn reset_fifo(&mut self) { 456 self.read_count = 0; 457 self.read_pos = 0; 458 459 /* Reset FIFO flags */ 460 self.flags.reset(); 461 } 462 463 pub fn can_receive(&self) -> bool { 464 // trace_pl011_can_receive(s->lcr, s->read_count, r); 465 self.read_count < self.fifo_depth() 466 } 467 468 pub fn event(&mut self, event: QEMUChrEvent) { 469 if event == bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.fifo_enabled() { 470 self.put_fifo(DATA_BREAK); 471 self.receive_status_error_clear.set_break_error(true); 472 } 473 } 474 475 #[inline] 476 pub fn fifo_enabled(&self) -> bool { 477 matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO) 478 } 479 480 #[inline] 481 pub fn loopback_enabled(&self) -> bool { 482 self.control.enable_loopback() 483 } 484 485 #[inline] 486 pub fn fifo_depth(&self) -> usize { 487 // Note: FIFO depth is expected to be power-of-2 488 if self.fifo_enabled() { 489 return PL011_FIFO_DEPTH; 490 } 491 1 492 } 493 494 pub fn put_fifo(&mut self, value: c_uint) { 495 let depth = self.fifo_depth(); 496 assert!(depth > 0); 497 let slot = (self.read_pos + self.read_count) & (depth - 1); 498 self.read_fifo[slot] = value; 499 self.read_count += 1; 500 self.flags.set_receive_fifo_empty(false); 501 if self.read_count == depth { 502 self.flags.set_receive_fifo_full(true); 503 } 504 505 if self.read_count == self.read_trigger { 506 self.int_level |= registers::INT_RX; 507 self.update(); 508 } 509 } 510 511 pub fn update(&self) { 512 let flags = self.int_level & self.int_enabled; 513 for (irq, i) in self.interrupts.iter().zip(IRQMASK) { 514 irq.set(flags & i != 0); 515 } 516 } 517 518 pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> { 519 /* Sanity-check input state */ 520 if self.read_pos >= self.read_fifo.len() || self.read_count > self.read_fifo.len() { 521 return Err(()); 522 } 523 524 if !self.fifo_enabled() && self.read_count > 0 && self.read_pos > 0 { 525 // Older versions of PL011 didn't ensure that the single 526 // character in the FIFO in FIFO-disabled mode is in 527 // element 0 of the array; convert to follow the current 528 // code's assumptions. 529 self.read_fifo[0] = self.read_fifo[self.read_pos]; 530 self.read_pos = 0; 531 } 532 533 self.ibrd &= IBRD_MASK; 534 self.fbrd &= FBRD_MASK; 535 536 Ok(()) 537 } 538 } 539 540 /// Which bits in the interrupt status matter for each outbound IRQ line ? 541 pub const IRQMASK: [u32; 6] = [ 542 /* combined IRQ */ 543 Interrupt::E 544 | Interrupt::MS 545 | Interrupt::RT as u32 546 | Interrupt::TX as u32 547 | Interrupt::RX as u32, 548 Interrupt::RX as u32, 549 Interrupt::TX as u32, 550 Interrupt::RT as u32, 551 Interrupt::MS, 552 Interrupt::E, 553 ]; 554 555 /// # Safety 556 /// 557 /// We expect the FFI user of this function to pass a valid pointer, that has 558 /// the same size as [`PL011State`]. We also expect the device is 559 /// readable/writeable from one thread at any time. 560 pub unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_int { 561 unsafe { 562 debug_assert!(!opaque.is_null()); 563 let state = NonNull::new_unchecked(opaque.cast::<PL011State>()); 564 state.as_ref().can_receive().into() 565 } 566 } 567 568 /// # Safety 569 /// 570 /// We expect the FFI user of this function to pass a valid pointer, that has 571 /// the same size as [`PL011State`]. We also expect the device is 572 /// readable/writeable from one thread at any time. 573 /// 574 /// The buffer and size arguments must also be valid. 575 pub unsafe extern "C" fn pl011_receive(opaque: *mut c_void, buf: *const u8, size: c_int) { 576 unsafe { 577 debug_assert!(!opaque.is_null()); 578 let mut state = NonNull::new_unchecked(opaque.cast::<PL011State>()); 579 if state.as_ref().loopback_enabled() { 580 return; 581 } 582 if size > 0 { 583 debug_assert!(!buf.is_null()); 584 state.as_mut().put_fifo(c_uint::from(buf.read_volatile())) 585 } 586 } 587 } 588 589 /// # Safety 590 /// 591 /// We expect the FFI user of this function to pass a valid pointer, that has 592 /// the same size as [`PL011State`]. We also expect the device is 593 /// readable/writeable from one thread at any time. 594 pub unsafe extern "C" fn pl011_event(opaque: *mut c_void, event: QEMUChrEvent) { 595 unsafe { 596 debug_assert!(!opaque.is_null()); 597 let mut state = NonNull::new_unchecked(opaque.cast::<PL011State>()); 598 state.as_mut().event(event) 599 } 600 } 601 602 /// # Safety 603 /// 604 /// We expect the FFI user of this function to pass a valid pointer for `chr`. 605 #[no_mangle] 606 pub unsafe extern "C" fn pl011_create( 607 addr: u64, 608 irq: qemu_irq, 609 chr: *mut Chardev, 610 ) -> *mut DeviceState { 611 unsafe { 612 let dev: *mut DeviceState = qdev_new(PL011State::TYPE_NAME.as_ptr()); 613 let sysbus: *mut SysBusDevice = dev.cast::<SysBusDevice>(); 614 615 qdev_prop_set_chr(dev, c_str!("chardev").as_ptr(), chr); 616 sysbus_realize_and_unref(sysbus, addr_of_mut!(error_fatal)); 617 sysbus_mmio_map(sysbus, 0, addr); 618 sysbus_connect_irq(sysbus, 0, irq); 619 dev 620 } 621 } 622 623 #[repr(C)] 624 #[derive(Debug, qemu_api_macros::Object)] 625 /// PL011 Luminary device model. 626 pub struct PL011Luminary { 627 parent_obj: PL011State, 628 } 629 630 #[repr(C)] 631 pub struct PL011LuminaryClass { 632 _inner: [u8; 0], 633 } 634 635 impl PL011Luminary { 636 /// Initializes a pre-allocated, unitialized instance of `PL011Luminary`. 637 /// 638 /// # Safety 639 /// 640 /// We expect the FFI user of this function to pass a valid pointer, that 641 /// has the same size as [`PL011Luminary`]. We also expect the device is 642 /// readable/writeable from one thread at any time. 643 unsafe fn init(&mut self) { 644 self.parent_obj.device_id = DeviceId::Luminary; 645 } 646 } 647 648 unsafe impl ObjectType for PL011Luminary { 649 type Class = PL011LuminaryClass; 650 const TYPE_NAME: &'static CStr = crate::TYPE_PL011_LUMINARY; 651 } 652 653 impl ObjectImpl for PL011Luminary { 654 type ParentType = PL011State; 655 656 const INSTANCE_INIT: Option<unsafe fn(&mut Self)> = Some(Self::init); 657 } 658 659 impl DeviceImpl for PL011Luminary {} 660 661 impl_device_class!(PL011Luminary); 662