10ac24d56SAlistair Francis /* 20ac24d56SAlistair Francis * QEMU RISC-V Boot Helper 30ac24d56SAlistair Francis * 40ac24d56SAlistair Francis * Copyright (c) 2017 SiFive, Inc. 50ac24d56SAlistair Francis * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 60ac24d56SAlistair Francis * 70ac24d56SAlistair Francis * This program is free software; you can redistribute it and/or modify it 80ac24d56SAlistair Francis * under the terms and conditions of the GNU General Public License, 90ac24d56SAlistair Francis * version 2 or later, as published by the Free Software Foundation. 100ac24d56SAlistair Francis * 110ac24d56SAlistair Francis * This program is distributed in the hope it will be useful, but WITHOUT 120ac24d56SAlistair Francis * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 130ac24d56SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 140ac24d56SAlistair Francis * more details. 150ac24d56SAlistair Francis * 160ac24d56SAlistair Francis * You should have received a copy of the GNU General Public License along with 170ac24d56SAlistair Francis * this program. If not, see <http://www.gnu.org/licenses/>. 180ac24d56SAlistair Francis */ 190ac24d56SAlistair Francis 200ac24d56SAlistair Francis #ifndef RISCV_BOOT_H 210ac24d56SAlistair Francis #define RISCV_BOOT_H 220ac24d56SAlistair Francis 23ec150c7eSMarkus Armbruster #include "exec/cpu-defs.h" 24757e99b1SAlistair Francis #include "hw/loader.h" 253ed2b8acSAlistair Francis #include "hw/riscv/riscv_hart.h" 26ec150c7eSMarkus Armbruster 27a0acd0a1SBin Meng #define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin" 28a0acd0a1SBin Meng #define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin" 29a0acd0a1SBin Meng 30a8259b53SAlistair Francis bool riscv_is_32bit(RISCVHartArrayState *harts); 31c4077842SAlistair Francis 32bf357e1dSAlistair Francis char *riscv_plic_hart_config_string(int hart_count); 33bf357e1dSAlistair Francis 34a8259b53SAlistair Francis target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, 3538bc4e34SAlistair Francis target_ulong firmware_end_addr); 36e66c531eSAlistair Francis target_ulong riscv_find_and_load_firmware(MachineState *machine, 37fdd1bda4SAlistair Francis const char *default_machine_firmware, 3802777ac3SAnup Patel hwaddr firmware_load_addr, 3902777ac3SAnup Patel symbol_fn_t sym_cb); 409d3f7108SDaniel Henrique Barboza const char *riscv_default_firmware_name(RISCVHartArrayState *harts); 41*8f619626SBin Meng char *riscv_find_firmware(const char *firmware_filename, 42*8f619626SBin Meng const char *default_machine_firmware); 43b3042223SAlistair Francis target_ulong riscv_load_firmware(const char *firmware_filename, 4402777ac3SAnup Patel hwaddr firmware_load_addr, 4502777ac3SAnup Patel symbol_fn_t sym_cb); 466478dd74SZhuang, Siwei (Data61, Kensington NSW) target_ulong riscv_load_kernel(const char *kernel_filename, 4738bc4e34SAlistair Francis target_ulong firmware_end_addr, 486478dd74SZhuang, Siwei (Data61, Kensington NSW) symbol_fn_t sym_cb); 490ac24d56SAlistair Francis hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, 500ac24d56SAlistair Francis uint64_t kernel_entry, hwaddr *start); 51faee5441SDylan Jhong uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); 52a8259b53SAlistair Francis void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, 533ed2b8acSAlistair Francis hwaddr saddr, 5478936771SAlistair Francis hwaddr rom_base, hwaddr rom_size, 5578936771SAlistair Francis uint64_t kernel_entry, 566934f15bSDaniel Henrique Barboza uint64_t fdt_load_addr); 5778936771SAlistair Francis void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, 5878936771SAlistair Francis hwaddr rom_size, 59dc144fe1SAtish Patra uint32_t reset_vec_size, 60dc144fe1SAtish Patra uint64_t kernel_entry); 61ad40be27SYifei Jiang void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr); 62a5b0249dSSunil V L void riscv_setup_firmware_boot(MachineState *machine); 630ac24d56SAlistair Francis 640ac24d56SAlistair Francis #endif /* RISCV_BOOT_H */ 65