1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * LoongArch 7A1000 I/O interrupt controller definitions 4 * Copyright (c) 2024 Loongson Technology Corporation Limited 5 */ 6 7 #ifndef HW_LOONGARCH_PIC_COMMON_H 8 #define HW_LOONGARCH_PIC_COMMON_H 9 10 #include "hw/pci-host/ls7a.h" 11 #include "hw/sysbus.h" 12 13 #define PCH_PIC_INT_ID_VAL 0x7000000UL 14 #define PCH_PIC_INT_ID_VER 0x1UL 15 #define PCH_PIC_INT_ID_LO 0x00 16 #define PCH_PIC_INT_ID_HI 0x04 17 #define PCH_PIC_INT_MASK_LO 0x20 18 #define PCH_PIC_INT_MASK_HI 0x24 19 #define PCH_PIC_HTMSI_EN_LO 0x40 20 #define PCH_PIC_HTMSI_EN_HI 0x44 21 #define PCH_PIC_INT_EDGE_LO 0x60 22 #define PCH_PIC_INT_EDGE_HI 0x64 23 #define PCH_PIC_INT_CLEAR_LO 0x80 24 #define PCH_PIC_INT_CLEAR_HI 0x84 25 #define PCH_PIC_AUTO_CTRL0_LO 0xc0 26 #define PCH_PIC_AUTO_CTRL0_HI 0xc4 27 #define PCH_PIC_AUTO_CTRL1_LO 0xe0 28 #define PCH_PIC_AUTO_CTRL1_HI 0xe4 29 #define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100 30 #define PCH_PIC_ROUTE_ENTRY_END 0x13f 31 #define PCH_PIC_HTMSI_VEC_OFFSET 0x200 32 #define PCH_PIC_HTMSI_VEC_END 0x23f 33 #define PCH_PIC_INT_STATUS_LO 0x3a0 34 #define PCH_PIC_INT_STATUS_HI 0x3a4 35 #define PCH_PIC_INT_POL_LO 0x3e0 36 #define PCH_PIC_INT_POL_HI 0x3e4 37 38 #define STATUS_LO_START 0 39 #define STATUS_HI_START 0x4 40 #define POL_LO_START 0x40 41 #define POL_HI_START 0x44 42 43 #define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common" 44 OBJECT_DECLARE_TYPE(LoongArchPICCommonState, 45 LoongArchPICCommonClass, LOONGARCH_PIC_COMMON) 46 47 struct LoongArchPICCommonState { 48 SysBusDevice parent_obj; 49 50 qemu_irq parent_irq[64]; 51 uint64_t int_mask; /* 0x020 interrupt mask register */ 52 uint64_t htmsi_en; /* 0x040 1=msi */ 53 uint64_t intedge; /* 0x060 edge=1 level=0 */ 54 uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */ 55 uint64_t auto_crtl0; /* 0x0c0 */ 56 uint64_t auto_crtl1; /* 0x0e0 */ 57 uint64_t last_intirr; /* edge detection */ 58 uint64_t intirr; /* 0x380 interrupt request register */ 59 uint64_t intisr; /* 0x3a0 interrupt service register */ 60 /* 61 * 0x3e0 interrupt level polarity selection 62 * register 0 for high level trigger 63 */ 64 uint64_t int_polarity; 65 66 uint8_t route_entry[64]; /* 0x100 - 0x138 */ 67 uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */ 68 69 MemoryRegion iomem32_low; 70 MemoryRegion iomem32_high; 71 MemoryRegion iomem8; 72 unsigned int irq_num; 73 }; 74 75 struct LoongArchPICCommonClass { 76 SysBusDeviceClass parent_class; 77 78 DeviceRealize parent_realize; 79 int (*pre_save)(LoongArchPICCommonState *s); 80 int (*post_load)(LoongArchPICCommonState *s, int version_id); 81 }; 82 #endif /* HW_LOONGARCH_PIC_COMMON_H */ 83