xref: /qemu/include/hw/intc/aspeed_intc.h (revision ab24c6a2df8e6c8055b6f1dfe80697320b327c50)
1 /*
2  * ASPEED INTC Controller
3  *
4  * Copyright (C) 2024 ASPEED Technology Inc.
5  *
6  * SPDX-License-Identifier: GPL-2.0-or-later
7  */
8 #ifndef ASPEED_INTC_H
9 #define ASPEED_INTC_H
10 
11 #include "hw/sysbus.h"
12 #include "qom/object.h"
13 #include "hw/or-irq.h"
14 
15 #define TYPE_ASPEED_INTC "aspeed.intc"
16 #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
17 OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
18 
19 #define ASPEED_INTC_MAX_INPINS 9
20 #define ASPEED_INTC_MAX_OUTPINS 9
21 
22 typedef struct AspeedINTCIRQ {
23     int inpin_idx;
24     int outpin_idx;
25     int num_outpins;
26     uint32_t enable_reg;
27     uint32_t status_reg;
28 } AspeedINTCIRQ;
29 
30 struct AspeedINTCState {
31     /*< private >*/
32     SysBusDevice parent_obj;
33 
34     /*< public >*/
35     MemoryRegion iomem;
36     MemoryRegion iomem_container;
37 
38     uint32_t *regs;
39     OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
40     qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
41 
42     uint32_t enable[ASPEED_INTC_MAX_INPINS];
43     uint32_t mask[ASPEED_INTC_MAX_INPINS];
44     uint32_t pending[ASPEED_INTC_MAX_INPINS];
45 };
46 
47 struct AspeedINTCClass {
48     SysBusDeviceClass parent_class;
49 
50     uint32_t num_lines;
51     uint32_t num_inpins;
52     uint32_t num_outpins;
53     uint64_t mem_size;
54     uint64_t nr_regs;
55     uint64_t reg_offset;
56     const MemoryRegionOps *reg_ops;
57     const AspeedINTCIRQ *irq_table;
58     int irq_table_count;
59 };
60 
61 #endif /* ASPEED_INTC_H */
62