1 /* 2 * ASPEED INTC Controller 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 #ifndef ASPEED_INTC_H 9 #define ASPEED_INTC_H 10 11 #include "hw/sysbus.h" 12 #include "qom/object.h" 13 #include "hw/or-irq.h" 14 15 #define TYPE_ASPEED_INTC "aspeed.intc" 16 #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" 17 #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700" 18 #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp" 19 #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp" 20 21 OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) 22 23 #define ASPEED_INTC_MAX_INPINS 10 24 #define ASPEED_INTC_MAX_OUTPINS 19 25 26 typedef struct AspeedINTCIRQ { 27 int inpin_idx; 28 int outpin_idx; 29 int num_outpins; 30 uint32_t enable_reg; 31 uint32_t status_reg; 32 } AspeedINTCIRQ; 33 34 struct AspeedINTCState { 35 /*< private >*/ 36 SysBusDevice parent_obj; 37 38 /*< public >*/ 39 MemoryRegion iomem; 40 MemoryRegion iomem_container; 41 42 uint32_t *regs; 43 OrIRQState orgates[ASPEED_INTC_MAX_INPINS]; 44 qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS]; 45 46 uint32_t enable[ASPEED_INTC_MAX_INPINS]; 47 uint32_t mask[ASPEED_INTC_MAX_INPINS]; 48 uint32_t pending[ASPEED_INTC_MAX_INPINS]; 49 }; 50 51 struct AspeedINTCClass { 52 SysBusDeviceClass parent_class; 53 54 uint32_t num_lines; 55 uint32_t num_inpins; 56 uint32_t num_outpins; 57 uint64_t mem_size; 58 uint64_t nr_regs; 59 uint64_t reg_offset; 60 const MemoryRegionOps *reg_ops; 61 const AspeedINTCIRQ *irq_table; 62 int irq_table_count; 63 }; 64 65 #endif /* ASPEED_INTC_H */ 66