xref: /qemu/include/hw/intc/aspeed_intc.h (revision 63f3618f9be0f28ff36cd4b5685877715b97e669)
1 /*
2  * ASPEED INTC Controller
3  *
4  * Copyright (C) 2024 ASPEED Technology Inc.
5  *
6  * SPDX-License-Identifier: GPL-2.0-or-later
7  */
8 #ifndef ASPEED_INTC_H
9 #define ASPEED_INTC_H
10 
11 #include "hw/sysbus.h"
12 #include "qom/object.h"
13 #include "hw/or-irq.h"
14 
15 #define TYPE_ASPEED_INTC "aspeed.intc"
16 #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
17 OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
18 
19 #define ASPEED_INTC_NR_INTS 9
20 #define ASPEED_INTC_MAX_INPINS 9
21 
22 struct AspeedINTCState {
23     /*< private >*/
24     SysBusDevice parent_obj;
25 
26     /*< public >*/
27     MemoryRegion iomem;
28     MemoryRegion iomem_container;
29 
30     uint32_t *regs;
31     OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
32     qemu_irq output_pins[ASPEED_INTC_NR_INTS];
33 
34     uint32_t enable[ASPEED_INTC_MAX_INPINS];
35     uint32_t mask[ASPEED_INTC_MAX_INPINS];
36     uint32_t pending[ASPEED_INTC_MAX_INPINS];
37 };
38 
39 struct AspeedINTCClass {
40     SysBusDeviceClass parent_class;
41 
42     uint32_t num_lines;
43     uint32_t num_inpins;
44     uint64_t mem_size;
45     uint64_t nr_regs;
46     uint64_t reg_offset;
47     const MemoryRegionOps *reg_ops;
48 };
49 
50 #endif /* ASPEED_INTC_H */
51