1d831c5fdSJamin Lin /* 2d831c5fdSJamin Lin * ASPEED INTC Controller 3d831c5fdSJamin Lin * 4d831c5fdSJamin Lin * Copyright (C) 2024 ASPEED Technology Inc. 5d831c5fdSJamin Lin * 6d831c5fdSJamin Lin * SPDX-License-Identifier: GPL-2.0-or-later 7d831c5fdSJamin Lin */ 8d831c5fdSJamin Lin #ifndef ASPEED_INTC_H 9d831c5fdSJamin Lin #define ASPEED_INTC_H 10d831c5fdSJamin Lin 11d831c5fdSJamin Lin #include "hw/sysbus.h" 12d831c5fdSJamin Lin #include "qom/object.h" 13d831c5fdSJamin Lin #include "hw/or-irq.h" 14d831c5fdSJamin Lin 15d831c5fdSJamin Lin #define TYPE_ASPEED_INTC "aspeed.intc" 16d831c5fdSJamin Lin #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" 1738ba38d8SJamin Lin #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700" 18*8872b671SSteven Lee #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp" 19*8872b671SSteven Lee #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp" 20*8872b671SSteven Lee 21d831c5fdSJamin Lin OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) 22d831c5fdSJamin Lin 239178ff91SJamin Lin #define ASPEED_INTC_MAX_INPINS 10 249178ff91SJamin Lin #define ASPEED_INTC_MAX_OUTPINS 19 25d831c5fdSJamin Lin 26ab24c6a2SJamin Lin typedef struct AspeedINTCIRQ { 27ab24c6a2SJamin Lin int inpin_idx; 28ab24c6a2SJamin Lin int outpin_idx; 29ab24c6a2SJamin Lin int num_outpins; 30ab24c6a2SJamin Lin uint32_t enable_reg; 31ab24c6a2SJamin Lin uint32_t status_reg; 32ab24c6a2SJamin Lin } AspeedINTCIRQ; 33ab24c6a2SJamin Lin 34d831c5fdSJamin Lin struct AspeedINTCState { 35d831c5fdSJamin Lin /*< private >*/ 36d831c5fdSJamin Lin SysBusDevice parent_obj; 37d831c5fdSJamin Lin 38d831c5fdSJamin Lin /*< public >*/ 39d831c5fdSJamin Lin MemoryRegion iomem; 40c5728c34SJamin Lin MemoryRegion iomem_container; 41c5728c34SJamin Lin 42563afea0SJamin Lin uint32_t *regs; 4363f3618fSJamin Lin OrIRQState orgates[ASPEED_INTC_MAX_INPINS]; 4435c909cdSJamin Lin qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS]; 45d831c5fdSJamin Lin 4663f3618fSJamin Lin uint32_t enable[ASPEED_INTC_MAX_INPINS]; 4763f3618fSJamin Lin uint32_t mask[ASPEED_INTC_MAX_INPINS]; 4863f3618fSJamin Lin uint32_t pending[ASPEED_INTC_MAX_INPINS]; 49d831c5fdSJamin Lin }; 50d831c5fdSJamin Lin 51d831c5fdSJamin Lin struct AspeedINTCClass { 52d831c5fdSJamin Lin SysBusDeviceClass parent_class; 53d831c5fdSJamin Lin 54d831c5fdSJamin Lin uint32_t num_lines; 5563f3618fSJamin Lin uint32_t num_inpins; 5635c909cdSJamin Lin uint32_t num_outpins; 57c5728c34SJamin Lin uint64_t mem_size; 58b008465dSJamin Lin uint64_t nr_regs; 597ffee511SJamin Lin uint64_t reg_offset; 6028194d5dSJamin Lin const MemoryRegionOps *reg_ops; 61ab24c6a2SJamin Lin const AspeedINTCIRQ *irq_table; 62ab24c6a2SJamin Lin int irq_table_count; 63d831c5fdSJamin Lin }; 64d831c5fdSJamin Lin 65d831c5fdSJamin Lin #endif /* ASPEED_INTC_H */ 66