1d831c5fdSJamin Lin /* 2d831c5fdSJamin Lin * ASPEED INTC Controller 3d831c5fdSJamin Lin * 4d831c5fdSJamin Lin * Copyright (C) 2024 ASPEED Technology Inc. 5d831c5fdSJamin Lin * 6d831c5fdSJamin Lin * SPDX-License-Identifier: GPL-2.0-or-later 7d831c5fdSJamin Lin */ 8d831c5fdSJamin Lin #ifndef ASPEED_INTC_H 9d831c5fdSJamin Lin #define ASPEED_INTC_H 10d831c5fdSJamin Lin 11d831c5fdSJamin Lin #include "hw/sysbus.h" 12d831c5fdSJamin Lin #include "qom/object.h" 13d831c5fdSJamin Lin #include "hw/or-irq.h" 14d831c5fdSJamin Lin 15d831c5fdSJamin Lin #define TYPE_ASPEED_INTC "aspeed.intc" 16d831c5fdSJamin Lin #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" 17d831c5fdSJamin Lin OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) 18d831c5fdSJamin Lin 19d831c5fdSJamin Lin #define ASPEED_INTC_NR_REGS (0x2000 >> 2) 20d831c5fdSJamin Lin #define ASPEED_INTC_NR_INTS 9 21d831c5fdSJamin Lin 22d831c5fdSJamin Lin struct AspeedINTCState { 23d831c5fdSJamin Lin /*< private >*/ 24d831c5fdSJamin Lin SysBusDevice parent_obj; 25d831c5fdSJamin Lin 26d831c5fdSJamin Lin /*< public >*/ 27d831c5fdSJamin Lin MemoryRegion iomem; 28c5728c34SJamin Lin MemoryRegion iomem_container; 29c5728c34SJamin Lin 30*563afea0SJamin Lin uint32_t *regs; 31d831c5fdSJamin Lin OrIRQState orgates[ASPEED_INTC_NR_INTS]; 32d831c5fdSJamin Lin qemu_irq output_pins[ASPEED_INTC_NR_INTS]; 33d831c5fdSJamin Lin 34d831c5fdSJamin Lin uint32_t enable[ASPEED_INTC_NR_INTS]; 35d831c5fdSJamin Lin uint32_t mask[ASPEED_INTC_NR_INTS]; 36d831c5fdSJamin Lin uint32_t pending[ASPEED_INTC_NR_INTS]; 37d831c5fdSJamin Lin }; 38d831c5fdSJamin Lin 39d831c5fdSJamin Lin struct AspeedINTCClass { 40d831c5fdSJamin Lin SysBusDeviceClass parent_class; 41d831c5fdSJamin Lin 42d831c5fdSJamin Lin uint32_t num_lines; 43d831c5fdSJamin Lin uint32_t num_ints; 44c5728c34SJamin Lin uint64_t mem_size; 45d831c5fdSJamin Lin }; 46d831c5fdSJamin Lin 47d831c5fdSJamin Lin #endif /* ASPEED_INTC_H */ 48