1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "exec/cpu-defs.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/riscv/boot.h" 28 #include "hw/riscv/boot_opensbi.h" 29 #include "elf.h" 30 #include "system/device_tree.h" 31 #include "system/qtest.h" 32 #include "system/kvm.h" 33 #include "system/reset.h" 34 35 #include <libfdt.h> 36 37 bool riscv_is_32bit(RISCVHartArrayState *harts) 38 { 39 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); 40 return mcc->misa_mxl_max == MXL_RV32; 41 } 42 43 /* 44 * Return the per-socket PLIC hart topology configuration string 45 * (caller must free with g_free()) 46 */ 47 char *riscv_plic_hart_config_string(int hart_count) 48 { 49 g_autofree const char **vals = g_new(const char *, hart_count + 1); 50 int i; 51 52 for (i = 0; i < hart_count; i++) { 53 CPUState *cs = qemu_get_cpu(i); 54 CPURISCVState *env = &RISCV_CPU(cs)->env; 55 56 if (kvm_enabled()) { 57 vals[i] = "S"; 58 } else if (riscv_has_ext(env, RVS)) { 59 vals[i] = "MS"; 60 } else { 61 vals[i] = "M"; 62 } 63 } 64 vals[i] = NULL; 65 66 /* g_strjoinv() obliges us to cast away const here */ 67 return g_strjoinv(",", (char **)vals); 68 } 69 70 void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts) 71 { 72 info->kernel_size = 0; 73 info->initrd_size = 0; 74 info->is_32bit = riscv_is_32bit(harts); 75 } 76 77 target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, 78 target_ulong firmware_end_addr) { 79 if (info->is_32bit) { 80 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 81 } else { 82 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 83 } 84 } 85 86 const char *riscv_default_firmware_name(RISCVHartArrayState *harts) 87 { 88 if (riscv_is_32bit(harts)) { 89 return RISCV32_BIOS_BIN; 90 } 91 92 return RISCV64_BIOS_BIN; 93 } 94 95 static char *riscv_find_bios(const char *bios_filename) 96 { 97 char *filename; 98 99 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename); 100 if (filename == NULL) { 101 if (!qtest_enabled()) { 102 /* 103 * We only ship OpenSBI binary bios images in the QEMU source. 104 * For machines that use images other than the default bios, 105 * running QEMU test will complain hence let's suppress the error 106 * report for QEMU testing. 107 */ 108 error_report("Unable to find the RISC-V BIOS \"%s\"", 109 bios_filename); 110 exit(1); 111 } 112 } 113 114 return filename; 115 } 116 117 char *riscv_find_firmware(const char *firmware_filename, 118 const char *default_machine_firmware) 119 { 120 char *filename = NULL; 121 122 if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) { 123 /* 124 * The user didn't specify -bios, or has specified "-bios default". 125 * That means we are going to load the OpenSBI binary included in 126 * the QEMU source. 127 */ 128 filename = riscv_find_bios(default_machine_firmware); 129 } else if (strcmp(firmware_filename, "none")) { 130 filename = riscv_find_bios(firmware_filename); 131 } 132 133 return filename; 134 } 135 136 target_ulong riscv_find_and_load_firmware(MachineState *machine, 137 const char *default_machine_firmware, 138 hwaddr *firmware_load_addr, 139 symbol_fn_t sym_cb) 140 { 141 char *firmware_filename; 142 target_ulong firmware_end_addr = *firmware_load_addr; 143 144 firmware_filename = riscv_find_firmware(machine->firmware, 145 default_machine_firmware); 146 147 if (firmware_filename) { 148 /* If not "none" load the firmware */ 149 firmware_end_addr = riscv_load_firmware(firmware_filename, 150 firmware_load_addr, sym_cb); 151 g_free(firmware_filename); 152 } 153 154 return firmware_end_addr; 155 } 156 157 target_ulong riscv_load_firmware(const char *firmware_filename, 158 hwaddr *firmware_load_addr, 159 symbol_fn_t sym_cb) 160 { 161 uint64_t firmware_entry, firmware_end; 162 ssize_t firmware_size; 163 164 g_assert(firmware_filename != NULL); 165 166 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 167 &firmware_entry, NULL, &firmware_end, NULL, 168 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 169 *firmware_load_addr = firmware_entry; 170 return firmware_end; 171 } 172 173 firmware_size = load_image_targphys_as(firmware_filename, 174 *firmware_load_addr, 175 current_machine->ram_size, NULL); 176 177 if (firmware_size > 0) { 178 return *firmware_load_addr + firmware_size; 179 } 180 181 error_report("could not load firmware '%s'", firmware_filename); 182 exit(1); 183 } 184 185 static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info) 186 { 187 const char *filename = machine->initrd_filename; 188 uint64_t mem_size = machine->ram_size; 189 void *fdt = machine->fdt; 190 hwaddr start, end; 191 ssize_t size; 192 193 g_assert(filename != NULL); 194 195 /* 196 * We want to put the initrd far enough into RAM that when the 197 * kernel is uncompressed it will not clobber the initrd. However 198 * on boards without much RAM we must ensure that we still leave 199 * enough room for a decent sized initrd, and on boards with large 200 * amounts of RAM, we put the initrd at 512MB to allow large kernels 201 * to boot. 202 * So for boards with less than 1GB of RAM we put the initrd 203 * halfway into RAM, and for boards with 1GB of RAM or more we put 204 * the initrd at 512MB. 205 */ 206 start = info->image_low_addr + MIN(mem_size / 2, 512 * MiB); 207 208 size = load_ramdisk(filename, start, mem_size - start); 209 if (size == -1) { 210 size = load_image_targphys(filename, start, mem_size - start); 211 if (size == -1) { 212 error_report("could not load ramdisk '%s'", filename); 213 exit(1); 214 } 215 } 216 217 info->initrd_start = start; 218 info->initrd_size = size; 219 220 /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ 221 if (fdt) { 222 end = start + size; 223 qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start); 224 qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end); 225 } 226 } 227 228 void riscv_load_kernel(MachineState *machine, 229 RISCVBootInfo *info, 230 target_ulong kernel_start_addr, 231 bool load_initrd, 232 symbol_fn_t sym_cb) 233 { 234 const char *kernel_filename = machine->kernel_filename; 235 ssize_t kernel_size; 236 void *fdt = machine->fdt; 237 238 g_assert(kernel_filename != NULL); 239 240 /* 241 * NB: Use low address not ELF entry point to ensure that the fw_dynamic 242 * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL 243 * behaviour, as well as fw_dynamic with a raw binary, all of which jump to 244 * the (expected) load address load address. This allows kernels to have 245 * separate SBI and ELF entry points (used by FreeBSD, for example). 246 */ 247 kernel_size = load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, 248 &info->image_low_addr, &info->image_high_addr, 249 NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb); 250 if (kernel_size > 0) { 251 info->kernel_size = kernel_size; 252 goto out; 253 } 254 255 kernel_size = load_uimage_as(kernel_filename, &info->image_low_addr, 256 NULL, NULL, NULL, NULL, NULL); 257 if (kernel_size > 0) { 258 info->kernel_size = kernel_size; 259 info->image_high_addr = info->image_low_addr + kernel_size; 260 goto out; 261 } 262 263 kernel_size = load_image_targphys_as(kernel_filename, kernel_start_addr, 264 current_machine->ram_size, NULL); 265 if (kernel_size > 0) { 266 info->kernel_size = kernel_size; 267 info->image_low_addr = kernel_start_addr; 268 info->image_high_addr = info->image_low_addr + kernel_size; 269 goto out; 270 } 271 272 error_report("could not load kernel '%s'", kernel_filename); 273 exit(1); 274 275 out: 276 /* 277 * For 32 bit CPUs 'image_low_addr' can be sign-extended by 278 * load_elf_ram_sym(). 279 */ 280 if (info->is_32bit) { 281 info->image_low_addr = extract64(info->image_low_addr, 0, 32); 282 } 283 284 if (load_initrd && machine->initrd_filename) { 285 riscv_load_initrd(machine, info); 286 } 287 288 if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { 289 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 290 machine->kernel_cmdline); 291 } 292 } 293 294 /* 295 * This function makes an assumption that the DRAM interval 296 * 'dram_base' + 'dram_size' is contiguous. 297 * 298 * Considering that 'dram_end' is the lowest value between 299 * the end of the DRAM block and MachineState->ram_size, the 300 * FDT location will vary according to 'dram_base': 301 * 302 * - if 'dram_base' is less that 3072 MiB, the FDT will be 303 * put at the lowest value between 3072 MiB and 'dram_end'; 304 * 305 * - if 'dram_base' is higher than 3072 MiB, the FDT will be 306 * put at 'dram_end'. 307 * 308 * The FDT is fdt_packed() during the calculation. 309 */ 310 uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, 311 MachineState *ms, RISCVBootInfo *info) 312 { 313 int ret = fdt_pack(ms->fdt); 314 hwaddr dram_end, temp; 315 int fdtsize; 316 uint64_t dtb_start, dtb_start_limit; 317 318 /* Should only fail if we've built a corrupted tree */ 319 g_assert(ret == 0); 320 321 fdtsize = fdt_totalsize(ms->fdt); 322 if (fdtsize <= 0) { 323 error_report("invalid device-tree"); 324 exit(1); 325 } 326 327 if (info->initrd_size) { 328 /* If initrd is successfully loaded, place DTB after it. */ 329 dtb_start_limit = info->initrd_start + info->initrd_size; 330 } else if (info->kernel_size) { 331 /* If only kernel is successfully loaded, place DTB after it. */ 332 dtb_start_limit = info->image_high_addr; 333 } else { 334 /* Otherwise, do not check DTB overlapping */ 335 dtb_start_limit = 0; 336 } 337 338 /* 339 * A dram_size == 0, usually from a MemMapEntry[].size element, 340 * means that the DRAM block goes all the way to ms->ram_size. 341 */ 342 dram_end = dram_base; 343 dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size; 344 345 /* 346 * We should put fdt as far as possible to avoid kernel/initrd overwriting 347 * its content. But it should be addressable by 32 bit system as well in RV32. 348 * Thus, put it near to the end of dram in RV64, and put it near to the end 349 * of dram or 3GB whichever is lesser in RV32. 350 */ 351 if (!info->is_32bit) { 352 temp = dram_end; 353 } else { 354 temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; 355 } 356 357 dtb_start = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 358 359 if (dtb_start_limit && (dtb_start < dtb_start_limit)) { 360 error_report("No enough memory to place DTB after kernel/initrd"); 361 exit(1); 362 } 363 364 return dtb_start; 365 } 366 367 /* 368 * 'fdt_addr' is received as hwaddr because boards might put 369 * the FDT beyond 32-bit addressing boundary. 370 */ 371 void riscv_load_fdt(hwaddr fdt_addr, void *fdt) 372 { 373 uint32_t fdtsize = fdt_totalsize(fdt); 374 375 /* copy in the device tree */ 376 qemu_fdt_dumpdtb(fdt, fdtsize); 377 378 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 379 &address_space_memory); 380 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 381 rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); 382 } 383 384 void riscv_rom_copy_firmware_info(MachineState *machine, 385 RISCVHartArrayState *harts, 386 hwaddr rom_base, hwaddr rom_size, 387 uint32_t reset_vec_size, 388 uint64_t kernel_entry) 389 { 390 struct fw_dynamic_info32 dinfo32; 391 struct fw_dynamic_info dinfo; 392 size_t dinfo_len; 393 394 if (riscv_is_32bit(harts)) { 395 dinfo32.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); 396 dinfo32.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); 397 dinfo32.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); 398 dinfo32.next_addr = cpu_to_le32(kernel_entry); 399 dinfo32.options = 0; 400 dinfo32.boot_hart = 0; 401 dinfo_len = sizeof(dinfo32); 402 } else { 403 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); 404 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); 405 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); 406 dinfo.next_addr = cpu_to_le64(kernel_entry); 407 dinfo.options = 0; 408 dinfo.boot_hart = 0; 409 dinfo_len = sizeof(dinfo); 410 } 411 412 /** 413 * copy the dynamic firmware info. This information is specific to 414 * OpenSBI but doesn't break any other firmware as long as they don't 415 * expect any certain value in "a2" register. 416 */ 417 if (dinfo_len > (rom_size - reset_vec_size)) { 418 error_report("not enough space to store dynamic firmware info"); 419 exit(1); 420 } 421 422 rom_add_blob_fixed_as("mrom.finfo", 423 riscv_is_32bit(harts) ? 424 (void *)&dinfo32 : (void *)&dinfo, 425 dinfo_len, 426 rom_base + reset_vec_size, 427 &address_space_memory); 428 } 429 430 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, 431 hwaddr start_addr, 432 hwaddr rom_base, hwaddr rom_size, 433 uint64_t kernel_entry, 434 uint64_t fdt_load_addr) 435 { 436 int i; 437 uint32_t start_addr_hi32 = 0x00000000; 438 uint32_t fdt_load_addr_hi32 = 0x00000000; 439 440 if (!riscv_is_32bit(harts)) { 441 start_addr_hi32 = start_addr >> 32; 442 fdt_load_addr_hi32 = fdt_load_addr >> 32; 443 } 444 /* reset vector */ 445 uint32_t reset_vec[10] = { 446 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 447 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 448 0xf1402573, /* csrr a0, mhartid */ 449 0, 450 0, 451 0x00028067, /* jr t0 */ 452 start_addr, /* start: .dword */ 453 start_addr_hi32, 454 fdt_load_addr, /* fdt_laddr: .dword */ 455 fdt_load_addr_hi32, 456 /* fw_dyn: */ 457 }; 458 if (riscv_is_32bit(harts)) { 459 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ 460 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ 461 } else { 462 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ 463 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ 464 } 465 466 if (!harts->harts[0].cfg.ext_zicsr) { 467 /* 468 * The Zicsr extension has been disabled, so let's ensure we don't 469 * run the CSR instruction. Let's fill the address with a non 470 * compressed nop. 471 */ 472 reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ 473 } 474 475 /* copy in the reset vector in little_endian byte order */ 476 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 477 reset_vec[i] = cpu_to_le32(reset_vec[i]); 478 } 479 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 480 rom_base, &address_space_memory); 481 riscv_rom_copy_firmware_info(machine, harts, 482 rom_base, rom_size, 483 sizeof(reset_vec), 484 kernel_entry); 485 } 486 487 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) 488 { 489 CPUState *cs; 490 491 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 492 RISCVCPU *riscv_cpu = RISCV_CPU(cs); 493 riscv_cpu->env.kernel_addr = kernel_addr; 494 riscv_cpu->env.fdt_addr = fdt_addr; 495 } 496 } 497 498 void riscv_setup_firmware_boot(MachineState *machine) 499 { 500 if (machine->kernel_filename) { 501 FWCfgState *fw_cfg; 502 fw_cfg = fw_cfg_find(); 503 504 assert(fw_cfg); 505 /* 506 * Expose the kernel, the command line, and the initrd in fw_cfg. 507 * We don't process them here at all, it's all left to the 508 * firmware. 509 */ 510 load_image_to_fw_cfg(fw_cfg, 511 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 512 machine->kernel_filename, 513 true); 514 load_image_to_fw_cfg(fw_cfg, 515 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 516 machine->initrd_filename, false); 517 518 if (machine->kernel_cmdline) { 519 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 520 strlen(machine->kernel_cmdline) + 1); 521 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 522 machine->kernel_cmdline); 523 } 524 } 525 } 526