1 /*
2 * QEMU RISC-V Boot Helper
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "exec/cpu-defs.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/riscv/boot.h"
28 #include "hw/riscv/boot_opensbi.h"
29 #include "elf.h"
30 #include "system/device_tree.h"
31 #include "system/qtest.h"
32 #include "system/kvm.h"
33 #include "system/reset.h"
34
35 #include <libfdt.h>
36
riscv_is_32bit(RISCVHartArrayState * harts)37 bool riscv_is_32bit(RISCVHartArrayState *harts)
38 {
39 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]);
40 return mcc->def->misa_mxl_max == MXL_RV32;
41 }
42
43 /*
44 * Return the per-socket PLIC hart topology configuration string
45 * (caller must free with g_free())
46 */
riscv_plic_hart_config_string(int hart_count)47 char *riscv_plic_hart_config_string(int hart_count)
48 {
49 g_autofree const char **vals = g_new(const char *, hart_count + 1);
50 int i;
51
52 for (i = 0; i < hart_count; i++) {
53 CPUState *cs = qemu_get_cpu(i);
54 CPURISCVState *env = &RISCV_CPU(cs)->env;
55
56 if (kvm_enabled()) {
57 vals[i] = "S";
58 } else if (riscv_has_ext(env, RVS)) {
59 vals[i] = "MS";
60 } else {
61 vals[i] = "M";
62 }
63 }
64 vals[i] = NULL;
65
66 /* g_strjoinv() obliges us to cast away const here */
67 return g_strjoinv(",", (char **)vals);
68 }
69
riscv_boot_info_init(RISCVBootInfo * info,RISCVHartArrayState * harts)70 void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)
71 {
72 info->kernel_size = 0;
73 info->initrd_size = 0;
74 info->is_32bit = riscv_is_32bit(harts);
75 }
76
riscv_calc_kernel_start_addr(RISCVBootInfo * info,target_ulong firmware_end_addr)77 target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
78 target_ulong firmware_end_addr) {
79 if (info->is_32bit) {
80 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
81 } else {
82 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
83 }
84 }
85
riscv_default_firmware_name(RISCVHartArrayState * harts)86 const char *riscv_default_firmware_name(RISCVHartArrayState *harts)
87 {
88 if (riscv_is_32bit(harts)) {
89 return RISCV32_BIOS_BIN;
90 }
91
92 return RISCV64_BIOS_BIN;
93 }
94
riscv_find_bios(const char * bios_filename)95 static char *riscv_find_bios(const char *bios_filename)
96 {
97 char *filename;
98
99 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename);
100 if (filename == NULL) {
101 if (!qtest_enabled()) {
102 /*
103 * We only ship OpenSBI binary bios images in the QEMU source.
104 * For machines that use images other than the default bios,
105 * running QEMU test will complain hence let's suppress the error
106 * report for QEMU testing.
107 */
108 error_report("Unable to find the RISC-V BIOS \"%s\"",
109 bios_filename);
110 exit(1);
111 }
112 }
113
114 return filename;
115 }
116
riscv_find_firmware(const char * firmware_filename,const char * default_machine_firmware)117 char *riscv_find_firmware(const char *firmware_filename,
118 const char *default_machine_firmware)
119 {
120 char *filename = NULL;
121
122 if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) {
123 /*
124 * The user didn't specify -bios, or has specified "-bios default".
125 * That means we are going to load the OpenSBI binary included in
126 * the QEMU source.
127 */
128 filename = riscv_find_bios(default_machine_firmware);
129 } else if (strcmp(firmware_filename, "none")) {
130 filename = riscv_find_bios(firmware_filename);
131 }
132
133 return filename;
134 }
135
riscv_find_and_load_firmware(MachineState * machine,const char * default_machine_firmware,hwaddr * firmware_load_addr,symbol_fn_t sym_cb)136 target_ulong riscv_find_and_load_firmware(MachineState *machine,
137 const char *default_machine_firmware,
138 hwaddr *firmware_load_addr,
139 symbol_fn_t sym_cb)
140 {
141 char *firmware_filename;
142 target_ulong firmware_end_addr = *firmware_load_addr;
143
144 firmware_filename = riscv_find_firmware(machine->firmware,
145 default_machine_firmware);
146
147 if (firmware_filename) {
148 /* If not "none" load the firmware */
149 firmware_end_addr = riscv_load_firmware(firmware_filename,
150 firmware_load_addr, sym_cb);
151 g_free(firmware_filename);
152 }
153
154 return firmware_end_addr;
155 }
156
riscv_load_firmware(const char * firmware_filename,hwaddr * firmware_load_addr,symbol_fn_t sym_cb)157 target_ulong riscv_load_firmware(const char *firmware_filename,
158 hwaddr *firmware_load_addr,
159 symbol_fn_t sym_cb)
160 {
161 uint64_t firmware_entry, firmware_end;
162 ssize_t firmware_size;
163
164 g_assert(firmware_filename != NULL);
165
166 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
167 &firmware_entry, NULL, &firmware_end, NULL,
168 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
169 *firmware_load_addr = firmware_entry;
170 return firmware_end;
171 }
172
173 firmware_size = load_image_targphys_as(firmware_filename,
174 *firmware_load_addr,
175 current_machine->ram_size, NULL);
176
177 if (firmware_size > 0) {
178 return *firmware_load_addr + firmware_size;
179 }
180
181 error_report("could not load firmware '%s'", firmware_filename);
182 exit(1);
183 }
184
riscv_load_initrd(MachineState * machine,RISCVBootInfo * info)185 static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info)
186 {
187 const char *filename = machine->initrd_filename;
188 uint64_t mem_size = machine->ram_size;
189 void *fdt = machine->fdt;
190 hwaddr start, end;
191 ssize_t size;
192
193 g_assert(filename != NULL);
194
195 /*
196 * We want to put the initrd far enough into RAM that when the
197 * kernel is uncompressed it will not clobber the initrd. However
198 * on boards without much RAM we must ensure that we still leave
199 * enough room for a decent sized initrd, and on boards with large
200 * amounts of RAM, we put the initrd at 512MB to allow large kernels
201 * to boot.
202 * So for boards with less than 1GB of RAM we put the initrd
203 * halfway into RAM, and for boards with 1GB of RAM or more we put
204 * the initrd at 512MB.
205 */
206 start = info->image_low_addr + MIN(mem_size / 2, 512 * MiB);
207
208 size = load_ramdisk(filename, start, mem_size - start);
209 if (size == -1) {
210 size = load_image_targphys(filename, start, mem_size - start);
211 if (size == -1) {
212 error_report("could not load ramdisk '%s'", filename);
213 exit(1);
214 }
215 }
216
217 info->initrd_start = start;
218 info->initrd_size = size;
219
220 /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
221 if (fdt) {
222 end = start + size;
223 qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
224 qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
225 }
226 }
227
riscv_load_kernel(MachineState * machine,RISCVBootInfo * info,target_ulong kernel_start_addr,bool load_initrd,symbol_fn_t sym_cb)228 void riscv_load_kernel(MachineState *machine,
229 RISCVBootInfo *info,
230 target_ulong kernel_start_addr,
231 bool load_initrd,
232 symbol_fn_t sym_cb)
233 {
234 const char *kernel_filename = machine->kernel_filename;
235 ssize_t kernel_size;
236 void *fdt = machine->fdt;
237
238 g_assert(kernel_filename != NULL);
239
240 /*
241 * NB: Use low address not ELF entry point to ensure that the fw_dynamic
242 * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL
243 * behaviour, as well as fw_dynamic with a raw binary, all of which jump to
244 * the (expected) load address load address. This allows kernels to have
245 * separate SBI and ELF entry points (used by FreeBSD, for example).
246 */
247 kernel_size = load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL,
248 &info->image_low_addr, &info->image_high_addr,
249 NULL, ELFDATA2LSB, EM_RISCV,
250 1, 0, NULL, true, sym_cb);
251 if (kernel_size > 0) {
252 info->kernel_size = kernel_size;
253 goto out;
254 }
255
256 kernel_size = load_uimage_as(kernel_filename, &info->image_low_addr,
257 NULL, NULL, NULL, NULL, NULL);
258 if (kernel_size > 0) {
259 info->kernel_size = kernel_size;
260 info->image_high_addr = info->image_low_addr + kernel_size;
261 goto out;
262 }
263
264 kernel_size = load_image_targphys_as(kernel_filename, kernel_start_addr,
265 current_machine->ram_size, NULL);
266 if (kernel_size > 0) {
267 info->kernel_size = kernel_size;
268 info->image_low_addr = kernel_start_addr;
269 info->image_high_addr = info->image_low_addr + kernel_size;
270 goto out;
271 }
272
273 error_report("could not load kernel '%s'", kernel_filename);
274 exit(1);
275
276 out:
277 /*
278 * For 32 bit CPUs 'image_low_addr' can be sign-extended by
279 * load_elf_ram_sym().
280 */
281 if (info->is_32bit) {
282 info->image_low_addr = extract64(info->image_low_addr, 0, 32);
283 }
284
285 if (load_initrd && machine->initrd_filename) {
286 riscv_load_initrd(machine, info);
287 }
288
289 if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
290 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
291 machine->kernel_cmdline);
292 }
293 }
294
295 /*
296 * This function makes an assumption that the DRAM interval
297 * 'dram_base' + 'dram_size' is contiguous.
298 *
299 * Considering that 'dram_end' is the lowest value between
300 * the end of the DRAM block and MachineState->ram_size, the
301 * FDT location will vary according to 'dram_base':
302 *
303 * - if 'dram_base' is less that 3072 MiB, the FDT will be
304 * put at the lowest value between 3072 MiB and 'dram_end';
305 *
306 * - if 'dram_base' is higher than 3072 MiB, the FDT will be
307 * put at 'dram_end'.
308 *
309 * The FDT is fdt_packed() during the calculation.
310 */
riscv_compute_fdt_addr(hwaddr dram_base,hwaddr dram_size,MachineState * ms,RISCVBootInfo * info)311 uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
312 MachineState *ms, RISCVBootInfo *info)
313 {
314 int ret = fdt_pack(ms->fdt);
315 hwaddr dram_end, temp;
316 int fdtsize;
317 uint64_t dtb_start, dtb_start_limit;
318
319 /* Should only fail if we've built a corrupted tree */
320 g_assert(ret == 0);
321
322 fdtsize = fdt_totalsize(ms->fdt);
323 if (fdtsize <= 0) {
324 error_report("invalid device-tree");
325 exit(1);
326 }
327
328 if (info->initrd_size) {
329 /* If initrd is successfully loaded, place DTB after it. */
330 dtb_start_limit = info->initrd_start + info->initrd_size;
331 } else if (info->kernel_size) {
332 /* If only kernel is successfully loaded, place DTB after it. */
333 dtb_start_limit = info->image_high_addr;
334 } else {
335 /* Otherwise, do not check DTB overlapping */
336 dtb_start_limit = 0;
337 }
338
339 /*
340 * A dram_size == 0, usually from a MemMapEntry[].size element,
341 * means that the DRAM block goes all the way to ms->ram_size.
342 */
343 dram_end = dram_base;
344 dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size;
345
346 /*
347 * We should put fdt as far as possible to avoid kernel/initrd overwriting
348 * its content. But it should be addressable by 32 bit system as well in RV32.
349 * Thus, put it near to the end of dram in RV64, and put it near to the end
350 * of dram or 3GB whichever is lesser in RV32.
351 */
352 if (!info->is_32bit) {
353 temp = dram_end;
354 } else {
355 temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
356 }
357
358 dtb_start = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
359
360 if (dtb_start_limit && (dtb_start < dtb_start_limit)) {
361 error_report("No enough memory to place DTB after kernel/initrd");
362 exit(1);
363 }
364
365 return dtb_start;
366 }
367
368 /*
369 * 'fdt_addr' is received as hwaddr because boards might put
370 * the FDT beyond 32-bit addressing boundary.
371 */
riscv_load_fdt(hwaddr fdt_addr,void * fdt)372 void riscv_load_fdt(hwaddr fdt_addr, void *fdt)
373 {
374 uint32_t fdtsize = fdt_totalsize(fdt);
375
376 /* copy in the device tree */
377 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
378 &address_space_memory);
379 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
380 rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));
381 }
382
riscv_rom_copy_firmware_info(MachineState * machine,RISCVHartArrayState * harts,hwaddr rom_base,hwaddr rom_size,uint32_t reset_vec_size,uint64_t kernel_entry)383 void riscv_rom_copy_firmware_info(MachineState *machine,
384 RISCVHartArrayState *harts,
385 hwaddr rom_base, hwaddr rom_size,
386 uint32_t reset_vec_size,
387 uint64_t kernel_entry)
388 {
389 struct fw_dynamic_info32 dinfo32;
390 struct fw_dynamic_info dinfo;
391 size_t dinfo_len;
392
393 if (riscv_is_32bit(harts)) {
394 dinfo32.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
395 dinfo32.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
396 dinfo32.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
397 dinfo32.next_addr = cpu_to_le32(kernel_entry);
398 dinfo32.options = 0;
399 dinfo32.boot_hart = 0;
400 dinfo_len = sizeof(dinfo32);
401 } else {
402 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
403 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
404 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
405 dinfo.next_addr = cpu_to_le64(kernel_entry);
406 dinfo.options = 0;
407 dinfo.boot_hart = 0;
408 dinfo_len = sizeof(dinfo);
409 }
410
411 /**
412 * copy the dynamic firmware info. This information is specific to
413 * OpenSBI but doesn't break any other firmware as long as they don't
414 * expect any certain value in "a2" register.
415 */
416 if (dinfo_len > (rom_size - reset_vec_size)) {
417 error_report("not enough space to store dynamic firmware info");
418 exit(1);
419 }
420
421 rom_add_blob_fixed_as("mrom.finfo",
422 riscv_is_32bit(harts) ?
423 (void *)&dinfo32 : (void *)&dinfo,
424 dinfo_len,
425 rom_base + reset_vec_size,
426 &address_space_memory);
427 }
428
riscv_setup_rom_reset_vec(MachineState * machine,RISCVHartArrayState * harts,hwaddr start_addr,hwaddr rom_base,hwaddr rom_size,uint64_t kernel_entry,uint64_t fdt_load_addr)429 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
430 hwaddr start_addr,
431 hwaddr rom_base, hwaddr rom_size,
432 uint64_t kernel_entry,
433 uint64_t fdt_load_addr)
434 {
435 int i;
436 uint32_t start_addr_hi32 = 0x00000000;
437 uint32_t fdt_load_addr_hi32 = 0x00000000;
438
439 if (!riscv_is_32bit(harts)) {
440 start_addr_hi32 = start_addr >> 32;
441 fdt_load_addr_hi32 = fdt_load_addr >> 32;
442 }
443 /* reset vector */
444 uint32_t reset_vec[10] = {
445 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
446 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
447 0xf1402573, /* csrr a0, mhartid */
448 0,
449 0,
450 0x00028067, /* jr t0 */
451 start_addr, /* start: .dword */
452 start_addr_hi32,
453 fdt_load_addr, /* fdt_laddr: .dword */
454 fdt_load_addr_hi32,
455 /* fw_dyn: */
456 };
457 if (riscv_is_32bit(harts)) {
458 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */
459 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */
460 } else {
461 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */
462 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
463 }
464
465 if (!harts->harts[0].cfg.ext_zicsr) {
466 /*
467 * The Zicsr extension has been disabled, so let's ensure we don't
468 * run the CSR instruction. Let's fill the address with a non
469 * compressed nop.
470 */
471 reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */
472 }
473
474 /* copy in the reset vector in little_endian byte order */
475 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
476 reset_vec[i] = cpu_to_le32(reset_vec[i]);
477 }
478 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
479 rom_base, &address_space_memory);
480 riscv_rom_copy_firmware_info(machine, harts,
481 rom_base, rom_size,
482 sizeof(reset_vec),
483 kernel_entry);
484 }
485
riscv_setup_direct_kernel(hwaddr kernel_addr,hwaddr fdt_addr)486 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
487 {
488 CPUState *cs;
489
490 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
491 RISCVCPU *riscv_cpu = RISCV_CPU(cs);
492 riscv_cpu->env.kernel_addr = kernel_addr;
493 riscv_cpu->env.fdt_addr = fdt_addr;
494 }
495 }
496
riscv_setup_firmware_boot(MachineState * machine)497 void riscv_setup_firmware_boot(MachineState *machine)
498 {
499 if (machine->kernel_filename) {
500 FWCfgState *fw_cfg;
501 fw_cfg = fw_cfg_find();
502
503 assert(fw_cfg);
504 /*
505 * Expose the kernel, the command line, and the initrd in fw_cfg.
506 * We don't process them here at all, it's all left to the
507 * firmware.
508 */
509 load_image_to_fw_cfg(fw_cfg,
510 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
511 machine->kernel_filename,
512 true);
513 load_image_to_fw_cfg(fw_cfg,
514 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
515 machine->initrd_filename, false);
516
517 if (machine->kernel_cmdline) {
518 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
519 strlen(machine->kernel_cmdline) + 1);
520 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
521 machine->kernel_cmdline);
522 }
523 }
524 }
525