1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/reset.h" 22 #include "sysemu/sysemu.h" 23 #include "qapi/error.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 #include "target/ppc/cpu.h" 27 #include "hw/ppc/ppc.h" 28 #include "hw/ppc/pnv.h" 29 #include "hw/ppc/pnv_core.h" 30 #include "hw/ppc/pnv_xscom.h" 31 #include "hw/ppc/xics.h" 32 #include "hw/qdev-properties.h" 33 34 static const char *pnv_core_cpu_typename(PnvCore *pc) 35 { 36 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc))); 37 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); 38 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type); 39 const char *cpu_type = object_class_get_name(object_class_by_name(s)); 40 g_free(s); 41 return cpu_type; 42 } 43 44 static void pnv_cpu_reset(void *opaque) 45 { 46 PowerPCCPU *cpu = opaque; 47 CPUState *cs = CPU(cpu); 48 CPUPPCState *env = &cpu->env; 49 50 cpu_reset(cs); 51 52 /* 53 * the skiboot firmware elects a primary thread to initialize the 54 * system and it can be any. 55 */ 56 env->gpr[3] = PNV_FDT_ADDR; 57 env->nip = 0x10; 58 env->msr |= MSR_HVB; /* Hypervisor mode */ 59 } 60 61 /* 62 * These values are read by the PowerNV HW monitors under Linux 63 */ 64 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 65 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 66 67 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, 68 unsigned int width) 69 { 70 uint32_t offset = addr >> 3; 71 uint64_t val = 0; 72 73 /* The result should be 38 C */ 74 switch (offset) { 75 case PNV_XSCOM_EX_DTS_RESULT0: 76 val = 0x26f024f023f0000ull; 77 break; 78 case PNV_XSCOM_EX_DTS_RESULT1: 79 val = 0x24f000000000000ull; 80 break; 81 default: 82 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", 83 addr); 84 } 85 86 return val; 87 } 88 89 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, 90 unsigned int width) 91 { 92 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", 93 addr); 94 } 95 96 static const MemoryRegionOps pnv_core_power8_xscom_ops = { 97 .read = pnv_core_power8_xscom_read, 98 .write = pnv_core_power8_xscom_write, 99 .valid.min_access_size = 8, 100 .valid.max_access_size = 8, 101 .impl.min_access_size = 8, 102 .impl.max_access_size = 8, 103 .endianness = DEVICE_BIG_ENDIAN, 104 }; 105 106 107 /* 108 * POWER9 core controls 109 */ 110 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d 111 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a 112 113 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, 114 unsigned int width) 115 { 116 uint32_t offset = addr >> 3; 117 uint64_t val = 0; 118 119 /* The result should be 38 C */ 120 switch (offset) { 121 case PNV_XSCOM_EX_DTS_RESULT0: 122 val = 0x26f024f023f0000ull; 123 break; 124 case PNV_XSCOM_EX_DTS_RESULT1: 125 val = 0x24f000000000000ull; 126 break; 127 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 128 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 129 val = 0x0; 130 break; 131 default: 132 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", 133 addr); 134 } 135 136 return val; 137 } 138 139 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 140 unsigned int width) 141 { 142 uint32_t offset = addr >> 3; 143 144 switch (offset) { 145 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 146 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 147 break; 148 default: 149 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", 150 addr); 151 } 152 } 153 154 static const MemoryRegionOps pnv_core_power9_xscom_ops = { 155 .read = pnv_core_power9_xscom_read, 156 .write = pnv_core_power9_xscom_write, 157 .valid.min_access_size = 8, 158 .valid.max_access_size = 8, 159 .impl.min_access_size = 8, 160 .impl.max_access_size = 8, 161 .endianness = DEVICE_BIG_ENDIAN, 162 }; 163 164 static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp) 165 { 166 CPUPPCState *env = &cpu->env; 167 int core_pir; 168 int thread_index = 0; /* TODO: TCG supports only one thread */ 169 ppc_spr_t *pir = &env->spr_cb[SPR_PIR]; 170 Error *local_err = NULL; 171 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 172 173 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 174 if (local_err) { 175 error_propagate(errp, local_err); 176 return; 177 } 178 179 pcc->intc_create(chip, cpu, &local_err); 180 if (local_err) { 181 error_propagate(errp, local_err); 182 return; 183 } 184 185 core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort); 186 187 /* 188 * The PIR of a thread is the core PIR + the thread index. We will 189 * need to find a way to get the thread index when TCG supports 190 * more than 1. We could use the object name ? 191 */ 192 pir->default_value = core_pir + thread_index; 193 194 /* Set time-base frequency to 512 MHz */ 195 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 196 197 qemu_register_reset(pnv_cpu_reset, cpu); 198 } 199 200 static void pnv_core_realize(DeviceState *dev, Error **errp) 201 { 202 PnvCore *pc = PNV_CORE(OBJECT(dev)); 203 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc); 204 CPUCore *cc = CPU_CORE(OBJECT(dev)); 205 const char *typename = pnv_core_cpu_typename(pc); 206 Error *local_err = NULL; 207 void *obj; 208 int i, j; 209 char name[32]; 210 Object *chip; 211 212 chip = object_property_get_link(OBJECT(dev), "chip", &local_err); 213 if (!chip) { 214 error_propagate_prepend(errp, local_err, 215 "required link 'chip' not found: "); 216 return; 217 } 218 219 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); 220 for (i = 0; i < cc->nr_threads; i++) { 221 PowerPCCPU *cpu; 222 223 obj = object_new(typename); 224 cpu = POWERPC_CPU(obj); 225 226 pc->threads[i] = POWERPC_CPU(obj); 227 228 snprintf(name, sizeof(name), "thread[%d]", i); 229 object_property_add_child(OBJECT(pc), name, obj, &error_abort); 230 object_property_add_alias(obj, "core-pir", OBJECT(pc), 231 "pir", &error_abort); 232 233 cpu->machine_data = g_new0(PnvCPUState, 1); 234 235 object_unref(obj); 236 } 237 238 for (j = 0; j < cc->nr_threads; j++) { 239 pnv_realize_vcpu(pc->threads[j], PNV_CHIP(chip), &local_err); 240 if (local_err) { 241 goto err; 242 } 243 } 244 245 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 246 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, 247 pc, name, PNV_XSCOM_EX_SIZE); 248 return; 249 250 err: 251 while (--i >= 0) { 252 obj = OBJECT(pc->threads[i]); 253 object_unparent(obj); 254 } 255 g_free(pc->threads); 256 error_propagate(errp, local_err); 257 } 258 259 static void pnv_unrealize_vcpu(PowerPCCPU *cpu) 260 { 261 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 262 263 qemu_unregister_reset(pnv_cpu_reset, cpu); 264 object_unparent(OBJECT(pnv_cpu_state(cpu)->intc)); 265 cpu_remove_sync(CPU(cpu)); 266 cpu->machine_data = NULL; 267 g_free(pnv_cpu); 268 object_unparent(OBJECT(cpu)); 269 } 270 271 static void pnv_core_unrealize(DeviceState *dev, Error **errp) 272 { 273 PnvCore *pc = PNV_CORE(dev); 274 CPUCore *cc = CPU_CORE(dev); 275 int i; 276 277 for (i = 0; i < cc->nr_threads; i++) { 278 pnv_unrealize_vcpu(pc->threads[i]); 279 } 280 g_free(pc->threads); 281 } 282 283 static Property pnv_core_properties[] = { 284 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0), 285 DEFINE_PROP_END_OF_LIST(), 286 }; 287 288 static void pnv_core_power8_class_init(ObjectClass *oc, void *data) 289 { 290 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 291 292 pcc->xscom_ops = &pnv_core_power8_xscom_ops; 293 } 294 295 static void pnv_core_power9_class_init(ObjectClass *oc, void *data) 296 { 297 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 298 299 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 300 } 301 302 static void pnv_core_class_init(ObjectClass *oc, void *data) 303 { 304 DeviceClass *dc = DEVICE_CLASS(oc); 305 306 dc->realize = pnv_core_realize; 307 dc->unrealize = pnv_core_unrealize; 308 dc->props = pnv_core_properties; 309 } 310 311 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ 312 { \ 313 .parent = TYPE_PNV_CORE, \ 314 .name = PNV_CORE_TYPE_NAME(cpu_model), \ 315 .class_init = pnv_core_##family##_class_init, \ 316 } 317 318 static const TypeInfo pnv_core_infos[] = { 319 { 320 .name = TYPE_PNV_CORE, 321 .parent = TYPE_CPU_CORE, 322 .instance_size = sizeof(PnvCore), 323 .class_size = sizeof(PnvCoreClass), 324 .class_init = pnv_core_class_init, 325 .abstract = true, 326 }, 327 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), 328 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), 329 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), 330 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), 331 }; 332 333 DEFINE_TYPES(pnv_core_infos) 334 335 /* 336 * POWER9 Quads 337 */ 338 339 #define P9X_EX_NCU_SPEC_BAR 0x11010 340 341 static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr, 342 unsigned int width) 343 { 344 uint32_t offset = addr >> 3; 345 uint64_t val = -1; 346 347 switch (offset) { 348 case P9X_EX_NCU_SPEC_BAR: 349 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 350 val = 0; 351 break; 352 default: 353 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, 354 offset); 355 } 356 357 return val; 358 } 359 360 static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val, 361 unsigned int width) 362 { 363 uint32_t offset = addr >> 3; 364 365 switch (offset) { 366 case P9X_EX_NCU_SPEC_BAR: 367 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 368 break; 369 default: 370 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, 371 offset); 372 } 373 } 374 375 static const MemoryRegionOps pnv_quad_xscom_ops = { 376 .read = pnv_quad_xscom_read, 377 .write = pnv_quad_xscom_write, 378 .valid.min_access_size = 8, 379 .valid.max_access_size = 8, 380 .impl.min_access_size = 8, 381 .impl.max_access_size = 8, 382 .endianness = DEVICE_BIG_ENDIAN, 383 }; 384 385 static void pnv_quad_realize(DeviceState *dev, Error **errp) 386 { 387 PnvQuad *eq = PNV_QUAD(dev); 388 char name[32]; 389 390 snprintf(name, sizeof(name), "xscom-quad.%d", eq->id); 391 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops, 392 eq, name, PNV9_XSCOM_EQ_SIZE); 393 } 394 395 static Property pnv_quad_properties[] = { 396 DEFINE_PROP_UINT32("id", PnvQuad, id, 0), 397 DEFINE_PROP_END_OF_LIST(), 398 }; 399 400 static void pnv_quad_class_init(ObjectClass *oc, void *data) 401 { 402 DeviceClass *dc = DEVICE_CLASS(oc); 403 404 dc->realize = pnv_quad_realize; 405 dc->props = pnv_quad_properties; 406 } 407 408 static const TypeInfo pnv_quad_info = { 409 .name = TYPE_PNV_QUAD, 410 .parent = TYPE_DEVICE, 411 .instance_size = sizeof(PnvQuad), 412 .class_init = pnv_quad_class_init, 413 }; 414 415 static void pnv_core_register_types(void) 416 { 417 type_register_static(&pnv_quad_info); 418 } 419 420 type_init(pnv_core_register_types) 421