1 /* 2 * Model of Petalogix linux reference design targeting Xilinx Spartan 3ADSP-1800 3 * boards. 4 * 5 * Copyright (c) 2009 Edgar E. Iglesias. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/units.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #include "hw/sysbus.h" 31 #include "net/net.h" 32 #include "hw/block/flash.h" 33 #include "system/system.h" 34 #include "hw/boards.h" 35 #include "hw/misc/unimp.h" 36 #include "exec/address-spaces.h" 37 #include "hw/char/xilinx_uartlite.h" 38 39 #include "boot.h" 40 41 #define LMB_BRAM_SIZE (128 * KiB) 42 #define FLASH_SIZE (16 * MiB) 43 44 #define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb" 45 46 #define MEMORY_BASEADDR 0x90000000 47 #define FLASH_BASEADDR 0xa0000000 48 #define GPIO_BASEADDR 0x81400000 49 #define INTC_BASEADDR 0x81800000 50 #define TIMER_BASEADDR 0x83c00000 51 #define UARTLITE_BASEADDR 0x84000000 52 #define ETHLITE_BASEADDR 0x81000000 53 54 #define TIMER_IRQ 0 55 #define ETHLITE_IRQ 1 56 #define UARTLITE_IRQ 3 57 58 #define TYPE_PETALOGIX_S3ADSP1800_MACHINE \ 59 MACHINE_TYPE_NAME("petalogix-s3adsp1800") 60 61 static void 62 petalogix_s3adsp1800_init(MachineState *machine) 63 { 64 ram_addr_t ram_size = machine->ram_size; 65 DeviceState *dev; 66 MicroBlazeCPU *cpu; 67 DriveInfo *dinfo; 68 int i; 69 hwaddr ddr_base = MEMORY_BASEADDR; 70 MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); 71 MemoryRegion *phys_ram = g_new(MemoryRegion, 1); 72 qemu_irq irq[32]; 73 MemoryRegion *sysmem = get_system_memory(); 74 EndianMode endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG 75 : ENDIAN_MODE_LITTLE; 76 77 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); 78 object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort); 79 object_property_set_bool(OBJECT(cpu), "little-endian", 80 !TARGET_BIG_ENDIAN, &error_abort); 81 qdev_realize(DEVICE(cpu), NULL, &error_abort); 82 83 /* Attach emulated BRAM through the LMB. */ 84 memory_region_init_ram(phys_lmb_bram, NULL, 85 "petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE, 86 &error_fatal); 87 memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram); 88 89 memory_region_init_ram(phys_ram, NULL, "petalogix_s3adsp1800.ram", 90 ram_size, &error_fatal); 91 memory_region_add_subregion(sysmem, ddr_base, phys_ram); 92 93 dinfo = drive_get(IF_PFLASH, 0, 0); 94 pflash_cfi01_register(FLASH_BASEADDR, 95 "petalogix_s3adsp1800.flash", FLASH_SIZE, 96 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 97 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); 98 99 dev = qdev_new("xlnx.xps-intc"); 100 qdev_prop_set_enum(dev, "endianness", endianness); 101 qdev_prop_set_uint32(dev, "kind-of-intr", 102 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ); 103 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 104 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 105 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 106 qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ)); 107 for (i = 0; i < 32; i++) { 108 irq[i] = qdev_get_gpio_in(dev, i); 109 } 110 111 dev = qdev_new(TYPE_XILINX_UARTLITE); 112 qdev_prop_set_enum(dev, "endianness", endianness); 113 qdev_prop_set_chr(dev, "chardev", serial_hd(0)); 114 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 115 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); 116 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]); 117 118 /* 2 timers at irq 2 @ 62 Mhz. */ 119 dev = qdev_new("xlnx.xps-timer"); 120 qdev_prop_set_enum(dev, "endianness", endianness); 121 qdev_prop_set_uint32(dev, "one-timer-only", 0); 122 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); 123 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 124 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 125 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 126 127 dev = qdev_new("xlnx.xps-ethernetlite"); 128 qdev_prop_set_enum(dev, "endianness", endianness); 129 qemu_configure_nic_device(dev, true, NULL); 130 qdev_prop_set_uint32(dev, "tx-ping-pong", 0); 131 qdev_prop_set_uint32(dev, "rx-ping-pong", 0); 132 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 133 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); 134 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); 135 136 create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000); 137 138 microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size, 139 machine->initrd_filename, 140 BINARY_DEVICE_TREE_FILE, 141 NULL); 142 } 143 144 static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void *data) 145 { 146 MachineClass *mc = MACHINE_CLASS(oc); 147 148 mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800"; 149 mc->init = petalogix_s3adsp1800_init; 150 mc->is_default = true; 151 } 152 153 static const TypeInfo petalogix_s3adsp1800_machine_types[] = { 154 { 155 .name = TYPE_PETALOGIX_S3ADSP1800_MACHINE, 156 .parent = TYPE_MACHINE, 157 .class_init = petalogix_s3adsp1800_machine_class_init, 158 }, 159 }; 160 161 DEFINE_TYPES(petalogix_s3adsp1800_machine_types) 162