1a72bd606SHelge Deller /* HPPA cores and system support chips. */ 24de43540SHelge Deller /* Be aware: QEMU and seabios-hppa repositories share this file as-is. */ 3a72bd606SHelge Deller 4f91005e1SMarkus Armbruster #ifndef HW_HPPA_HPPA_HARDWARE_H 5f91005e1SMarkus Armbruster #define HW_HPPA_HPPA_HARDWARE_H 6f91005e1SMarkus Armbruster 7a72bd606SHelge Deller #define FIRMWARE_START 0xf0000000 8a72bd606SHelge Deller #define FIRMWARE_END 0xf0800000 9*3f8c3d7bSHelge Deller #define FIRMWARE_HIGH 0xfffffff0 /* upper 32-bits of 64-bit firmware address */ 10*3f8c3d7bSHelge Deller 11*3f8c3d7bSHelge Deller #define RAM_MAP_HIGH 0x0100000000 /* memory above 3.75 GB is mapped here */ 12*3f8c3d7bSHelge Deller 13*3f8c3d7bSHelge Deller #define MEM_PDC_ENTRY 0x4800 /* PDC entry address */ 14a72bd606SHelge Deller 15a72bd606SHelge Deller #define DEVICE_HPA_LEN 0x00100000 16a72bd606SHelge Deller 17a72bd606SHelge Deller #define GSC_HPA 0xffc00000 18a72bd606SHelge Deller #define DINO_HPA 0xfff80000 19a72bd606SHelge Deller #define DINO_UART_HPA 0xfff83000 20a72bd606SHelge Deller #define DINO_UART_BASE 0xfff83800 21a72bd606SHelge Deller #define DINO_SCSI_HPA 0xfff8c000 22a72bd606SHelge Deller #define LASI_HPA 0xffd00000 23a72bd606SHelge Deller #define LASI_UART_HPA 0xffd05000 24a72bd606SHelge Deller #define LASI_SCSI_HPA 0xffd06000 25a72bd606SHelge Deller #define LASI_LAN_HPA 0xffd07000 26*3f8c3d7bSHelge Deller #define LASI_RTC_HPA 0xffd09000 27a72bd606SHelge Deller #define LASI_LPT_HPA 0xffd02000 28a72bd606SHelge Deller #define LASI_AUDIO_HPA 0xffd04000 29a72bd606SHelge Deller #define LASI_PS2KBD_HPA 0xffd08000 30a72bd606SHelge Deller #define LASI_PS2MOU_HPA 0xffd08100 31a72bd606SHelge Deller #define LASI_GFX_HPA 0xf8000000 324765384cSSven Schnelle #define ARTIST_FB_ADDR 0xf9000000 332b42f31eSHelge Deller #define CPU_HPA 0xfffb0000 3487e126eaSHelge Deller #define MEMORY_HPA 0xfffff000 35a72bd606SHelge Deller 36a72bd606SHelge Deller #define IDE_HPA 0xf9000000 /* Boot disc controller */ 37*3f8c3d7bSHelge Deller #define ASTRO_HPA 0xfed00000 38*3f8c3d7bSHelge Deller #define ELROY0_HPA 0xfed30000 39*3f8c3d7bSHelge Deller #define ELROY2_HPA 0xfed32000 40*3f8c3d7bSHelge Deller #define ELROY8_HPA 0xfed38000 41*3f8c3d7bSHelge Deller #define ELROYc_HPA 0xfed3c000 42*3f8c3d7bSHelge Deller #define ASTRO_MEMORY_HPA 0xfed10200 43*3f8c3d7bSHelge Deller 44*3f8c3d7bSHelge Deller #define SCSI_HPA 0xf1040000 /* emulated SCSI, needs to be in f region */ 45a72bd606SHelge Deller 464de43540SHelge Deller /* offsets to DINO HPA: */ 474de43540SHelge Deller #define DINO_PCI_ADDR 0x064 484de43540SHelge Deller #define DINO_CONFIG_DATA 0x068 494de43540SHelge Deller #define DINO_IO_DATA 0x06c 504de43540SHelge Deller 51*3f8c3d7bSHelge Deller #define PORT_PCI_CMD hppa_port_pci_cmd 52*3f8c3d7bSHelge Deller #define PORT_PCI_DATA hppa_port_pci_data 53a72bd606SHelge Deller 5424576007SHelge Deller #define FW_CFG_IO_BASE 0xfffa0000 55e3a99a8aSHelge Deller 565079892dSHelge Deller #define PORT_SERIAL1 (LASI_UART_HPA + 0x800) 575079892dSHelge Deller #define PORT_SERIAL2 (DINO_UART_HPA + 0x800) 58a72bd606SHelge Deller 5987e126eaSHelge Deller #define HPPA_MAX_CPUS 16 /* max. number of SMP CPUs */ 60a72bd606SHelge Deller #define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */ 61f91005e1SMarkus Armbruster 62*3f8c3d7bSHelge Deller #define CR_PSW_DEFAULT 6 /* used by SeaBIOS & QEMU for default PSW */ 63e3a99a8aSHelge Deller #define CPU_HPA_CR_REG 7 /* store CPU HPA in cr7 (SeaBIOS internal) */ 6487e126eaSHelge Deller #define PIM_STORAGE_SIZE 600 /* storage size of pdc_pim_toc_struct (64bit) */ 65e3a99a8aSHelge Deller 66*3f8c3d7bSHelge Deller #define ASTRO_BUS_MODULE 0x0a /* C3700: 0x0a, others maybe 0 ? */ 67*3f8c3d7bSHelge Deller 68*3f8c3d7bSHelge Deller /* ASTRO Memory and I/O regions */ 69*3f8c3d7bSHelge Deller #define ASTRO_BASE_HPA 0xfffed00000 70*3f8c3d7bSHelge Deller #define ELROY0_BASE_HPA 0xfffed30000 /* ELROY0_HPA */ 71*3f8c3d7bSHelge Deller 72*3f8c3d7bSHelge Deller #define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */ 73*3f8c3d7bSHelge Deller 74*3f8c3d7bSHelge Deller #define LMMIO_DIRECT0_BASE 0x300 75*3f8c3d7bSHelge Deller #define LMMIO_DIRECT0_MASK 0x308 76*3f8c3d7bSHelge Deller #define LMMIO_DIRECT0_ROUTE 0x310 77*3f8c3d7bSHelge Deller 78*3f8c3d7bSHelge Deller /* space register hashing */ 79*3f8c3d7bSHelge Deller #define HPPA64_DIAG_SPHASH_ENABLE 0x200 /* DIAG_SPHASH_ENAB (bit 54) */ 80*3f8c3d7bSHelge Deller #define HPPA64_PDC_CACHE_RET_SPID_VAL 0xfe0 /* PDC return value on 64-bit CPU */ 81d0ad4118SHelge Deller 82f91005e1SMarkus Armbruster #endif 83