1 /* 2 * Cortex-A9MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2009 CodeSourcery. 5 * Copyright (c) 2011 Linaro Limited. 6 * Written by Paul Brook, Peter Maydell. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "qemu/module.h" 14 #include "hw/cpu/a9mpcore.h" 15 #include "hw/irq.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/core/cpu.h" 18 #include "target/arm/cpu-qom.h" 19 20 #define A9_GIC_NUM_PRIORITY_BITS 5 21 22 static void a9mp_priv_set_irq(void *opaque, int irq, int level) 23 { 24 A9MPPrivState *s = (A9MPPrivState *)opaque; 25 26 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 27 } 28 29 static void a9mp_priv_initfn(Object *obj) 30 { 31 A9MPPrivState *s = A9MPCORE_PRIV(obj); 32 33 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); 34 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); 35 36 object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU); 37 38 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); 39 40 object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER); 41 42 object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); 43 44 object_initialize_child(obj, "wdt", &s->wdt, TYPE_ARM_MPTIMER); 45 } 46 47 static void a9mp_priv_realize(DeviceState *dev, Error **errp) 48 { 49 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 50 A9MPPrivState *s = A9MPCORE_PRIV(dev); 51 DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; 52 SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, 53 *wdtbusdev; 54 int i; 55 bool has_el3; 56 CPUState *cpu0; 57 Object *cpuobj; 58 59 if (s->num_irq < 32 || s->num_irq > 256) { 60 error_setg(errp, "Property 'num-irq' must be between 32 and 256"); 61 return; 62 } 63 64 cpu0 = qemu_get_cpu(0); 65 cpuobj = OBJECT(cpu0); 66 if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) { 67 /* We might allow Cortex-A5 once we model it */ 68 error_setg(errp, 69 "Cortex-A9MPCore peripheral can only use Cortex-A9 CPU"); 70 return; 71 } 72 73 scudev = DEVICE(&s->scu); 74 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 75 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 76 return; 77 } 78 scubusdev = SYS_BUS_DEVICE(&s->scu); 79 80 gicdev = DEVICE(&s->gic); 81 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 82 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 83 qdev_prop_set_uint32(gicdev, "num-priority-bits", 84 A9_GIC_NUM_PRIORITY_BITS); 85 86 /* Make the GIC's TZ support match the CPUs. We assume that 87 * either all the CPUs have TZ, or none do. 88 */ 89 has_el3 = object_property_find(cpuobj, "has_el3") && 90 object_property_get_bool(cpuobj, "has_el3", &error_abort); 91 qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); 92 93 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 94 return; 95 } 96 gicbusdev = SYS_BUS_DEVICE(&s->gic); 97 98 /* Pass through outbound IRQ lines from the GIC */ 99 sysbus_pass_irq(sbd, gicbusdev); 100 101 /* Pass through inbound GPIO lines to the GIC */ 102 qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); 103 104 gtimerdev = DEVICE(&s->gtimer); 105 qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); 106 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gtimer), errp)) { 107 return; 108 } 109 gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); 110 111 mptimerdev = DEVICE(&s->mptimer); 112 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 113 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), errp)) { 114 return; 115 } 116 mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); 117 118 wdtdev = DEVICE(&s->wdt); 119 qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); 120 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt), errp)) { 121 return; 122 } 123 wdtbusdev = SYS_BUS_DEVICE(&s->wdt); 124 125 /* Memory map (addresses are offsets from PERIPHBASE): 126 * 0x0000-0x00ff -- Snoop Control Unit 127 * 0x0100-0x01ff -- GIC CPU interface 128 * 0x0200-0x02ff -- Global Timer 129 * 0x0300-0x05ff -- nothing 130 * 0x0600-0x06ff -- private timers and watchdogs 131 * 0x0700-0x0fff -- nothing 132 * 0x1000-0x1fff -- GIC Distributor 133 */ 134 memory_region_add_subregion(&s->container, 0, 135 sysbus_mmio_get_region(scubusdev, 0)); 136 /* GIC CPU interface */ 137 memory_region_add_subregion(&s->container, 0x100, 138 sysbus_mmio_get_region(gicbusdev, 1)); 139 memory_region_add_subregion(&s->container, 0x200, 140 sysbus_mmio_get_region(gtimerbusdev, 0)); 141 /* Note that the A9 exposes only the "timer/watchdog for this core" 142 * memory region, not the "timer/watchdog for core X" ones 11MPcore has. 143 */ 144 memory_region_add_subregion(&s->container, 0x600, 145 sysbus_mmio_get_region(mptimerbusdev, 0)); 146 memory_region_add_subregion(&s->container, 0x620, 147 sysbus_mmio_get_region(wdtbusdev, 0)); 148 memory_region_add_subregion(&s->container, 0x1000, 149 sysbus_mmio_get_region(gicbusdev, 0)); 150 151 /* Wire up the interrupt from each watchdog and timer. 152 * For each core the global timer is PPI 27, the private 153 * timer is PPI 29 and the watchdog PPI 30. 154 */ 155 for (i = 0; i < s->num_cpu; i++) { 156 int ppibase = (s->num_irq - 32) + i * 32; 157 sysbus_connect_irq(gtimerbusdev, i, 158 qdev_get_gpio_in(gicdev, ppibase + 27)); 159 sysbus_connect_irq(mptimerbusdev, i, 160 qdev_get_gpio_in(gicdev, ppibase + 29)); 161 sysbus_connect_irq(wdtbusdev, i, 162 qdev_get_gpio_in(gicdev, ppibase + 30)); 163 } 164 } 165 166 static const Property a9mp_priv_properties[] = { 167 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), 168 /* 169 * The Cortex-A9MP may have anything from 0 to 224 external interrupt 170 * lines, plus always 32 internal IRQs. This property sets the total 171 * of internal + external, so the valid range is from 32 to 256. 172 * The board model must set this to whatever the configuration 173 * used for the CPU on that board or SoC is. 174 */ 175 DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 0), 176 }; 177 178 static void a9mp_priv_class_init(ObjectClass *klass, void *data) 179 { 180 DeviceClass *dc = DEVICE_CLASS(klass); 181 182 dc->realize = a9mp_priv_realize; 183 device_class_set_props(dc, a9mp_priv_properties); 184 } 185 186 static const TypeInfo a9mp_types[] = { 187 { 188 .name = TYPE_A9MPCORE_PRIV, 189 .parent = TYPE_SYS_BUS_DEVICE, 190 .instance_size = sizeof(A9MPPrivState), 191 .instance_init = a9mp_priv_initfn, 192 .class_init = a9mp_priv_class_init, 193 }, 194 }; 195 196 DEFINE_TYPES(a9mp_types) 197