1 /* 2 * QEMU CPU model (system specific) 3 * 4 * Copyright (c) 2012-2014 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "exec/address-spaces.h" 24 #include "exec/cputlb.h" 25 #include "exec/memory.h" 26 #include "exec/tb-flush.h" 27 #include "exec/tswap.h" 28 #include "hw/qdev-core.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/core/sysemu-cpu-ops.h" 31 #include "migration/vmstate.h" 32 #include "system/tcg.h" 33 34 bool cpu_has_work(CPUState *cpu) 35 { 36 g_assert(cpu->cc->has_work); 37 return cpu->cc->has_work(cpu); 38 } 39 40 bool cpu_paging_enabled(const CPUState *cpu) 41 { 42 if (cpu->cc->sysemu_ops->get_paging_enabled) { 43 return cpu->cc->sysemu_ops->get_paging_enabled(cpu); 44 } 45 46 return false; 47 } 48 49 bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 50 Error **errp) 51 { 52 if (cpu->cc->sysemu_ops->get_memory_mapping) { 53 return cpu->cc->sysemu_ops->get_memory_mapping(cpu, list, errp); 54 } 55 56 error_setg(errp, "Obtaining memory mappings is unsupported on this CPU."); 57 return false; 58 } 59 60 hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 61 MemTxAttrs *attrs) 62 { 63 hwaddr paddr; 64 65 if (cpu->cc->sysemu_ops->get_phys_page_attrs_debug) { 66 paddr = cpu->cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, 67 attrs); 68 } else { 69 /* Fallback for CPUs which don't implement the _attrs_ hook */ 70 *attrs = MEMTXATTRS_UNSPECIFIED; 71 paddr = cpu->cc->sysemu_ops->get_phys_page_debug(cpu, addr); 72 } 73 /* Indicate that this is a debug access. */ 74 attrs->debug = 1; 75 return paddr; 76 } 77 78 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) 79 { 80 MemTxAttrs attrs = {}; 81 82 return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); 83 } 84 85 int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) 86 { 87 int ret = 0; 88 89 if (cpu->cc->sysemu_ops->asidx_from_attrs) { 90 ret = cpu->cc->sysemu_ops->asidx_from_attrs(cpu, attrs); 91 assert(ret < cpu->num_ases && ret >= 0); 92 } 93 return ret; 94 } 95 96 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 97 void *opaque) 98 { 99 if (!cpu->cc->sysemu_ops->write_elf32_qemunote) { 100 return 0; 101 } 102 return (*cpu->cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque); 103 } 104 105 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 106 int cpuid, void *opaque) 107 { 108 if (!cpu->cc->sysemu_ops->write_elf32_note) { 109 return -1; 110 } 111 return (*cpu->cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque); 112 } 113 114 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 115 void *opaque) 116 { 117 if (!cpu->cc->sysemu_ops->write_elf64_qemunote) { 118 return 0; 119 } 120 return (*cpu->cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque); 121 } 122 123 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 124 int cpuid, void *opaque) 125 { 126 if (!cpu->cc->sysemu_ops->write_elf64_note) { 127 return -1; 128 } 129 return (*cpu->cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque); 130 } 131 132 bool cpu_virtio_is_big_endian(CPUState *cpu) 133 { 134 if (cpu->cc->sysemu_ops->virtio_is_big_endian) { 135 return cpu->cc->sysemu_ops->virtio_is_big_endian(cpu); 136 } 137 return target_words_bigendian(); 138 } 139 140 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) 141 { 142 GuestPanicInformation *res = NULL; 143 144 if (cpu->cc->sysemu_ops->get_crash_info) { 145 res = cpu->cc->sysemu_ops->get_crash_info(cpu); 146 } 147 return res; 148 } 149 150 static const Property cpu_system_props[] = { 151 /* 152 * Create a memory property for system CPU object, so users can 153 * wire up its memory. The default if no link is set up is to use 154 * the system address space. 155 */ 156 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, 157 MemoryRegion *), 158 }; 159 160 static bool cpu_get_start_powered_off(Object *obj, Error **errp) 161 { 162 CPUState *cpu = CPU(obj); 163 return cpu->start_powered_off; 164 } 165 166 static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp) 167 { 168 CPUState *cpu = CPU(obj); 169 cpu->start_powered_off = value; 170 } 171 172 void cpu_class_init_props(DeviceClass *dc) 173 { 174 ObjectClass *oc = OBJECT_CLASS(dc); 175 176 /* 177 * We can't use DEFINE_PROP_BOOL in the Property array for this 178 * property, because we want this to be settable after realize. 179 */ 180 object_class_property_add_bool(oc, "start-powered-off", 181 cpu_get_start_powered_off, 182 cpu_set_start_powered_off); 183 184 device_class_set_props(dc, cpu_system_props); 185 } 186 187 void cpu_exec_initfn(CPUState *cpu) 188 { 189 cpu->memory = get_system_memory(); 190 object_ref(OBJECT(cpu->memory)); 191 } 192 193 static int cpu_common_post_load(void *opaque, int version_id) 194 { 195 if (tcg_enabled()) { 196 CPUState *cpu = opaque; 197 198 /* 199 * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the 200 * version_id is increased. 201 */ 202 cpu->interrupt_request &= ~0x01; 203 204 tlb_flush(cpu); 205 206 /* 207 * loadvm has just updated the content of RAM, bypassing the 208 * usual mechanisms that ensure we flush TBs for writes to 209 * memory we've translated code from. So we must flush all TBs, 210 * which will now be stale. 211 */ 212 tb_flush(cpu); 213 } 214 215 return 0; 216 } 217 218 static int cpu_common_pre_load(void *opaque) 219 { 220 CPUState *cpu = opaque; 221 222 cpu->exception_index = -1; 223 224 return 0; 225 } 226 227 static bool cpu_common_exception_index_needed(void *opaque) 228 { 229 CPUState *cpu = opaque; 230 231 return tcg_enabled() && cpu->exception_index != -1; 232 } 233 234 static const VMStateDescription vmstate_cpu_common_exception_index = { 235 .name = "cpu_common/exception_index", 236 .version_id = 1, 237 .minimum_version_id = 1, 238 .needed = cpu_common_exception_index_needed, 239 .fields = (const VMStateField[]) { 240 VMSTATE_INT32(exception_index, CPUState), 241 VMSTATE_END_OF_LIST() 242 } 243 }; 244 245 static bool cpu_common_crash_occurred_needed(void *opaque) 246 { 247 CPUState *cpu = opaque; 248 249 return cpu->crash_occurred; 250 } 251 252 static const VMStateDescription vmstate_cpu_common_crash_occurred = { 253 .name = "cpu_common/crash_occurred", 254 .version_id = 1, 255 .minimum_version_id = 1, 256 .needed = cpu_common_crash_occurred_needed, 257 .fields = (const VMStateField[]) { 258 VMSTATE_BOOL(crash_occurred, CPUState), 259 VMSTATE_END_OF_LIST() 260 } 261 }; 262 263 const VMStateDescription vmstate_cpu_common = { 264 .name = "cpu_common", 265 .version_id = 1, 266 .minimum_version_id = 1, 267 .pre_load = cpu_common_pre_load, 268 .post_load = cpu_common_post_load, 269 .fields = (const VMStateField[]) { 270 VMSTATE_UINT32(halted, CPUState), 271 VMSTATE_UINT32(interrupt_request, CPUState), 272 VMSTATE_END_OF_LIST() 273 }, 274 .subsections = (const VMStateDescription * const []) { 275 &vmstate_cpu_common_exception_index, 276 &vmstate_cpu_common_crash_occurred, 277 NULL 278 } 279 }; 280 281 void cpu_vmstate_register(CPUState *cpu) 282 { 283 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { 284 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); 285 } 286 if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) { 287 vmstate_register(NULL, cpu->cpu_index, 288 cpu->cc->sysemu_ops->legacy_vmsd, cpu); 289 } 290 } 291 292 void cpu_vmstate_unregister(CPUState *cpu) 293 { 294 if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) { 295 vmstate_unregister(NULL, cpu->cc->sysemu_ops->legacy_vmsd, cpu); 296 } 297 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { 298 vmstate_unregister(NULL, &vmstate_cpu_common, cpu); 299 } 300 } 301