1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "hw/boards.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/kvm.h" 27 #include "sysemu/sysemu.h" 28 #include "kvm_arm.h" 29 30 #define GIC_NUM_SPI_INTR 160 31 32 #define ARM_PHYS_TIMER_PPI 30 33 #define ARM_VIRT_TIMER_PPI 27 34 #define ARM_HYP_TIMER_PPI 26 35 #define ARM_SEC_TIMER_PPI 29 36 #define GIC_MAINTENANCE_PPI 25 37 38 #define GEM_REVISION 0x40070106 39 40 #define GIC_BASE_ADDR 0xf9000000 41 #define GIC_DIST_ADDR 0xf9010000 42 #define GIC_CPU_ADDR 0xf9020000 43 #define GIC_VIFACE_ADDR 0xf9040000 44 #define GIC_VCPU_ADDR 0xf9060000 45 46 #define SATA_INTR 133 47 #define SATA_ADDR 0xFD0C0000 48 #define SATA_NUM_PORTS 2 49 50 #define QSPI_ADDR 0xff0f0000 51 #define LQSPI_ADDR 0xc0000000 52 #define QSPI_IRQ 15 53 54 #define DP_ADDR 0xfd4a0000 55 #define DP_IRQ 113 56 57 #define DPDMA_ADDR 0xfd4c0000 58 #define DPDMA_IRQ 116 59 60 #define IPI_ADDR 0xFF300000 61 #define IPI_IRQ 64 62 63 #define RTC_ADDR 0xffa60000 64 #define RTC_IRQ 26 65 66 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 67 68 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 69 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 70 }; 71 72 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 73 57, 59, 61, 63, 74 }; 75 76 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 77 0xFF000000, 0xFF010000, 78 }; 79 80 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 81 21, 22, 82 }; 83 84 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 85 0xFF160000, 0xFF170000, 86 }; 87 88 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 89 48, 49, 90 }; 91 92 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 93 0xFF040000, 0xFF050000, 94 }; 95 96 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 97 19, 20, 98 }; 99 100 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 101 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 102 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 103 }; 104 105 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 106 124, 125, 126, 127, 128, 129, 130, 131 107 }; 108 109 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 110 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 111 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 112 }; 113 114 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 115 77, 78, 79, 80, 81, 82, 83, 84 116 }; 117 118 typedef struct XlnxZynqMPGICRegion { 119 int region_index; 120 uint32_t address; 121 uint32_t offset; 122 bool virt; 123 } XlnxZynqMPGICRegion; 124 125 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 126 /* Distributor */ 127 { 128 .region_index = 0, 129 .address = GIC_DIST_ADDR, 130 .offset = 0, 131 .virt = false 132 }, 133 134 /* CPU interface */ 135 { 136 .region_index = 1, 137 .address = GIC_CPU_ADDR, 138 .offset = 0, 139 .virt = false 140 }, 141 { 142 .region_index = 1, 143 .address = GIC_CPU_ADDR + 0x10000, 144 .offset = 0x1000, 145 .virt = false 146 }, 147 148 /* Virtual interface */ 149 { 150 .region_index = 2, 151 .address = GIC_VIFACE_ADDR, 152 .offset = 0, 153 .virt = true 154 }, 155 156 /* Virtual CPU interface */ 157 { 158 .region_index = 3, 159 .address = GIC_VCPU_ADDR, 160 .offset = 0, 161 .virt = true 162 }, 163 { 164 .region_index = 3, 165 .address = GIC_VCPU_ADDR + 0x10000, 166 .offset = 0x1000, 167 .virt = true 168 }, 169 }; 170 171 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 172 { 173 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 174 } 175 176 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, 177 const char *boot_cpu, Error **errp) 178 { 179 Error *err = NULL; 180 int i; 181 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, 182 XLNX_ZYNQMP_NUM_RPU_CPUS); 183 184 if (num_rpus <= 0) { 185 /* Don't create rpu-cluster object if there's nothing to put in it */ 186 return; 187 } 188 189 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, 190 TYPE_CPU_CLUSTER); 191 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); 192 193 for (i = 0; i < num_rpus; i++) { 194 char *name; 195 196 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", 197 &s->rpu_cpu[i], 198 ARM_CPU_TYPE_NAME("cortex-r5f")); 199 200 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 201 if (strcmp(name, boot_cpu)) { 202 /* Secondary CPUs start in PSCI powered-down state */ 203 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 204 "start-powered-off", &error_abort); 205 } else { 206 s->boot_cpu_ptr = &s->rpu_cpu[i]; 207 } 208 g_free(name); 209 210 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 211 &error_abort); 212 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 213 &err); 214 if (err) { 215 error_propagate(errp, err); 216 return; 217 } 218 } 219 220 qdev_init_nofail(DEVICE(&s->rpu_cluster)); 221 } 222 223 static void xlnx_zynqmp_init(Object *obj) 224 { 225 MachineState *ms = MACHINE(qdev_get_machine()); 226 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 227 int i; 228 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 229 230 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, 231 TYPE_CPU_CLUSTER); 232 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); 233 234 for (i = 0; i < num_apus; i++) { 235 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", 236 &s->apu_cpu[i], 237 ARM_CPU_TYPE_NAME("cortex-a53")); 238 } 239 240 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); 241 242 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 243 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); 244 } 245 246 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 247 object_initialize_child(obj, "uart[*]", &s->uart[i], 248 TYPE_CADENCE_UART); 249 } 250 251 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); 252 253 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 254 sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci[i], 255 sizeof(s->sdhci[i]), TYPE_SYSBUS_SDHCI); 256 } 257 258 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 259 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS); 260 } 261 262 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS); 263 264 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP); 265 266 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA); 267 268 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI); 269 270 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC); 271 272 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 273 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA); 274 } 275 276 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 277 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA); 278 } 279 } 280 281 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 282 { 283 MachineState *ms = MACHINE(qdev_get_machine()); 284 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 285 MemoryRegion *system_memory = get_system_memory(); 286 uint8_t i; 287 uint64_t ram_size; 288 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 289 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 290 ram_addr_t ddr_low_size, ddr_high_size; 291 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 292 Error *err = NULL; 293 294 ram_size = memory_region_size(s->ddr_ram); 295 296 /* Create the DDR Memory Regions. User friendly checks should happen at 297 * the board level 298 */ 299 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 300 /* The RAM size is above the maximum available for the low DDR. 301 * Create the high DDR memory region as well. 302 */ 303 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 304 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 305 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 306 307 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev), 308 "ddr-ram-high", s->ddr_ram, ddr_low_size, 309 ddr_high_size); 310 memory_region_add_subregion(get_system_memory(), 311 XLNX_ZYNQMP_HIGH_RAM_START, 312 &s->ddr_ram_high); 313 } else { 314 /* RAM must be non-zero */ 315 assert(ram_size); 316 ddr_low_size = ram_size; 317 } 318 319 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low", 320 s->ddr_ram, 0, ddr_low_size); 321 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 322 323 /* Create the four OCM banks */ 324 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 325 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 326 327 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 328 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 329 memory_region_add_subregion(get_system_memory(), 330 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 331 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 332 &s->ocm_ram[i]); 333 334 g_free(ocm_name); 335 } 336 337 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 338 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 339 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 340 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); 341 qdev_prop_set_bit(DEVICE(&s->gic), 342 "has-virtualization-extensions", s->virt); 343 344 qdev_init_nofail(DEVICE(&s->apu_cluster)); 345 346 /* Realize APUs before realizing the GIC. KVM requires this. */ 347 for (i = 0; i < num_apus; i++) { 348 char *name; 349 350 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 351 "psci-conduit", &error_abort); 352 353 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 354 if (strcmp(name, boot_cpu)) { 355 /* Secondary CPUs start in PSCI powered-down state */ 356 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 357 "start-powered-off", &error_abort); 358 } else { 359 s->boot_cpu_ptr = &s->apu_cpu[i]; 360 } 361 g_free(name); 362 363 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 364 s->secure, "has_el3", NULL); 365 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 366 s->virt, "has_el2", NULL); 367 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 368 "reset-cbar", &error_abort); 369 object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus, 370 "core-count", &error_abort); 371 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 372 &err); 373 if (err) { 374 error_propagate(errp, err); 375 return; 376 } 377 } 378 379 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err); 380 if (err) { 381 error_propagate(errp, err); 382 return; 383 } 384 385 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 386 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 387 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 388 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 389 MemoryRegion *mr; 390 uint32_t addr = r->address; 391 int j; 392 393 if (r->virt && !s->virt) { 394 continue; 395 } 396 397 mr = sysbus_mmio_get_region(gic, r->region_index); 398 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 399 MemoryRegion *alias = &s->gic_mr[i][j]; 400 401 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 402 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); 403 memory_region_add_subregion(system_memory, addr, alias); 404 405 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 406 } 407 } 408 409 for (i = 0; i < num_apus; i++) { 410 qemu_irq irq; 411 412 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 413 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 414 ARM_CPU_IRQ)); 415 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, 416 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 417 ARM_CPU_FIQ)); 418 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, 419 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 420 ARM_CPU_VIRQ)); 421 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, 422 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 423 ARM_CPU_VFIQ)); 424 irq = qdev_get_gpio_in(DEVICE(&s->gic), 425 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 426 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); 427 irq = qdev_get_gpio_in(DEVICE(&s->gic), 428 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 429 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); 430 irq = qdev_get_gpio_in(DEVICE(&s->gic), 431 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); 432 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); 433 irq = qdev_get_gpio_in(DEVICE(&s->gic), 434 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); 435 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); 436 437 if (s->virt) { 438 irq = qdev_get_gpio_in(DEVICE(&s->gic), 439 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); 440 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); 441 } 442 } 443 444 if (s->has_rpu) { 445 info_report("The 'has_rpu' property is no longer required, to use the " 446 "RPUs just use -smp 6."); 447 } 448 449 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); 450 if (err) { 451 error_propagate(errp, err); 452 return; 453 } 454 455 if (!s->boot_cpu_ptr) { 456 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 457 return; 458 } 459 460 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 461 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 462 } 463 464 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 465 NICInfo *nd = &nd_table[i]; 466 467 if (nd->used) { 468 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 469 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 470 } 471 object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", 472 &error_abort); 473 object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", 474 &error_abort); 475 sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), &err); 476 if (err) { 477 error_propagate(errp, err); 478 return; 479 } 480 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 481 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 482 gic_spi[gem_intr[i]]); 483 } 484 485 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 486 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 487 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err); 488 if (err) { 489 error_propagate(errp, err); 490 return; 491 } 492 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 493 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 494 gic_spi[uart_intr[i]]); 495 } 496 497 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 498 &error_abort); 499 sysbus_realize(SYS_BUS_DEVICE(&s->sata), &err); 500 if (err) { 501 error_propagate(errp, err); 502 return; 503 } 504 505 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 506 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 507 508 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 509 char *bus_name; 510 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 511 Object *sdhci = OBJECT(&s->sdhci[i]); 512 513 /* Compatible with: 514 * - SD Host Controller Specification Version 3.00 515 * - SDIO Specification Version 3.0 516 * - eMMC Specification Version 4.51 517 */ 518 object_property_set_uint(sdhci, 3, "sd-spec-version", &err); 519 if (err) { 520 error_propagate(errp, err); 521 return; 522 } 523 object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err); 524 if (err) { 525 error_propagate(errp, err); 526 return; 527 } 528 object_property_set_uint(sdhci, UHS_I, "uhs", &err); 529 if (err) { 530 error_propagate(errp, err); 531 return; 532 } 533 object_property_set_bool(sdhci, true, "realized", &err); 534 if (err) { 535 error_propagate(errp, err); 536 return; 537 } 538 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 539 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 540 541 /* Alias controller SD bus to the SoC itself */ 542 bus_name = g_strdup_printf("sd-bus%d", i); 543 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus"); 544 g_free(bus_name); 545 } 546 547 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 548 gchar *bus_name; 549 550 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err); 551 if (err) { 552 error_propagate(errp, err); 553 return; 554 } 555 556 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 557 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 558 gic_spi[spi_intr[i]]); 559 560 /* Alias controller SPI bus to the SoC itself */ 561 bus_name = g_strdup_printf("spi%d", i); 562 object_property_add_alias(OBJECT(s), bus_name, 563 OBJECT(&s->spi[i]), "spi0"); 564 g_free(bus_name); 565 } 566 567 sysbus_realize(SYS_BUS_DEVICE(&s->qspi), &err); 568 if (err) { 569 error_propagate(errp, err); 570 return; 571 } 572 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 573 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 574 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); 575 576 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 577 gchar *bus_name; 578 gchar *target_bus; 579 580 /* Alias controller SPI bus to the SoC itself */ 581 bus_name = g_strdup_printf("qspi%d", i); 582 target_bus = g_strdup_printf("spi%d", i); 583 object_property_add_alias(OBJECT(s), bus_name, 584 OBJECT(&s->qspi), target_bus); 585 g_free(bus_name); 586 g_free(target_bus); 587 } 588 589 sysbus_realize(SYS_BUS_DEVICE(&s->dp), &err); 590 if (err) { 591 error_propagate(errp, err); 592 return; 593 } 594 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 595 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 596 597 sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), &err); 598 if (err) { 599 error_propagate(errp, err); 600 return; 601 } 602 object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", 603 &error_abort); 604 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 605 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 606 607 sysbus_realize(SYS_BUS_DEVICE(&s->ipi), &err); 608 if (err) { 609 error_propagate(errp, err); 610 return; 611 } 612 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 613 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 614 615 sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err); 616 if (err) { 617 error_propagate(errp, err); 618 return; 619 } 620 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 621 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 622 623 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 624 object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err); 625 if (err) { 626 error_propagate(errp, err); 627 return; 628 } 629 sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), &err); 630 if (err) { 631 error_propagate(errp, err); 632 return; 633 } 634 635 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 636 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 637 gic_spi[gdma_ch_intr[i]]); 638 } 639 640 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 641 sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), &err); 642 if (err) { 643 error_propagate(errp, err); 644 return; 645 } 646 647 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 648 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 649 gic_spi[adma_ch_intr[i]]); 650 } 651 } 652 653 static Property xlnx_zynqmp_props[] = { 654 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 655 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 656 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 657 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 658 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 659 MemoryRegion *), 660 DEFINE_PROP_END_OF_LIST() 661 }; 662 663 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 664 { 665 DeviceClass *dc = DEVICE_CLASS(oc); 666 667 device_class_set_props(dc, xlnx_zynqmp_props); 668 dc->realize = xlnx_zynqmp_realize; 669 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 670 dc->user_creatable = false; 671 } 672 673 static const TypeInfo xlnx_zynqmp_type_info = { 674 .name = TYPE_XLNX_ZYNQMP, 675 .parent = TYPE_DEVICE, 676 .instance_size = sizeof(XlnxZynqMPState), 677 .instance_init = xlnx_zynqmp_init, 678 .class_init = xlnx_zynqmp_class_init, 679 }; 680 681 static void xlnx_zynqmp_register_types(void) 682 { 683 type_register_static(&xlnx_zynqmp_type_info); 684 } 685 686 type_init(xlnx_zynqmp_register_types) 687