1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "hw/arm/xlnx-zynqmp.h" 22 #include "hw/intc/arm_gic_common.h" 23 #include "hw/misc/unimp.h" 24 #include "hw/boards.h" 25 #include "sysemu/kvm.h" 26 #include "sysemu/sysemu.h" 27 #include "kvm_arm.h" 28 29 #define GIC_NUM_SPI_INTR 160 30 31 #define ARM_PHYS_TIMER_PPI 30 32 #define ARM_VIRT_TIMER_PPI 27 33 #define ARM_HYP_TIMER_PPI 26 34 #define ARM_SEC_TIMER_PPI 29 35 #define GIC_MAINTENANCE_PPI 25 36 37 #define GEM_REVISION 0x40070106 38 39 #define GIC_BASE_ADDR 0xf9000000 40 #define GIC_DIST_ADDR 0xf9010000 41 #define GIC_CPU_ADDR 0xf9020000 42 #define GIC_VIFACE_ADDR 0xf9040000 43 #define GIC_VCPU_ADDR 0xf9060000 44 45 #define SATA_INTR 133 46 #define SATA_ADDR 0xFD0C0000 47 #define SATA_NUM_PORTS 2 48 49 #define QSPI_ADDR 0xff0f0000 50 #define LQSPI_ADDR 0xc0000000 51 #define QSPI_IRQ 15 52 #define QSPI_DMA_ADDR 0xff0f0800 53 #define NUM_QSPI_IRQ_LINES 2 54 55 #define DP_ADDR 0xfd4a0000 56 #define DP_IRQ 113 57 58 #define DPDMA_ADDR 0xfd4c0000 59 #define DPDMA_IRQ 116 60 61 #define APU_ADDR 0xfd5c0000 62 #define APU_SIZE 0x100 63 64 #define IPI_ADDR 0xFF300000 65 #define IPI_IRQ 64 66 67 #define RTC_ADDR 0xffa60000 68 #define RTC_IRQ 26 69 70 #define BBRAM_ADDR 0xffcd0000 71 #define BBRAM_IRQ 11 72 73 #define EFUSE_ADDR 0xffcc0000 74 #define EFUSE_IRQ 87 75 76 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 77 78 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 79 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 80 }; 81 82 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 83 57, 59, 61, 63, 84 }; 85 86 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 87 0xFF000000, 0xFF010000, 88 }; 89 90 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 91 21, 22, 92 }; 93 94 static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = { 95 0xFF060000, 0xFF070000, 96 }; 97 98 static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = { 99 23, 24, 100 }; 101 102 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 103 0xFF160000, 0xFF170000, 104 }; 105 106 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 107 48, 49, 108 }; 109 110 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 111 0xFF040000, 0xFF050000, 112 }; 113 114 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 115 19, 20, 116 }; 117 118 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 119 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 120 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 121 }; 122 123 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 124 124, 125, 126, 127, 128, 129, 130, 131 125 }; 126 127 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 128 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 129 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 130 }; 131 132 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 133 77, 78, 79, 80, 81, 82, 83, 84 134 }; 135 136 typedef struct XlnxZynqMPGICRegion { 137 int region_index; 138 uint32_t address; 139 uint32_t offset; 140 bool virt; 141 } XlnxZynqMPGICRegion; 142 143 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 144 /* Distributor */ 145 { 146 .region_index = 0, 147 .address = GIC_DIST_ADDR, 148 .offset = 0, 149 .virt = false 150 }, 151 152 /* CPU interface */ 153 { 154 .region_index = 1, 155 .address = GIC_CPU_ADDR, 156 .offset = 0, 157 .virt = false 158 }, 159 { 160 .region_index = 1, 161 .address = GIC_CPU_ADDR + 0x10000, 162 .offset = 0x1000, 163 .virt = false 164 }, 165 166 /* Virtual interface */ 167 { 168 .region_index = 2, 169 .address = GIC_VIFACE_ADDR, 170 .offset = 0, 171 .virt = true 172 }, 173 174 /* Virtual CPU interface */ 175 { 176 .region_index = 3, 177 .address = GIC_VCPU_ADDR, 178 .offset = 0, 179 .virt = true 180 }, 181 { 182 .region_index = 3, 183 .address = GIC_VCPU_ADDR + 0x10000, 184 .offset = 0x1000, 185 .virt = true 186 }, 187 }; 188 189 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 190 { 191 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 192 } 193 194 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, 195 const char *boot_cpu, Error **errp) 196 { 197 int i; 198 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, 199 XLNX_ZYNQMP_NUM_RPU_CPUS); 200 201 if (num_rpus <= 0) { 202 /* Don't create rpu-cluster object if there's nothing to put in it */ 203 return; 204 } 205 206 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, 207 TYPE_CPU_CLUSTER); 208 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); 209 210 for (i = 0; i < num_rpus; i++) { 211 const char *name; 212 213 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", 214 &s->rpu_cpu[i], 215 ARM_CPU_TYPE_NAME("cortex-r5f")); 216 217 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 218 if (strcmp(name, boot_cpu)) { 219 /* Secondary CPUs start in PSCI powered-down state */ 220 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), 221 "start-powered-off", true, &error_abort); 222 } else { 223 s->boot_cpu_ptr = &s->rpu_cpu[i]; 224 } 225 226 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true, 227 &error_abort); 228 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) { 229 return; 230 } 231 } 232 233 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal); 234 } 235 236 static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic) 237 { 238 SysBusDevice *sbd; 239 240 object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram, 241 sizeof(s->bbram), TYPE_XLNX_BBRAM, 242 &error_fatal, 243 "crc-zpads", "1", 244 NULL); 245 sbd = SYS_BUS_DEVICE(&s->bbram); 246 247 sysbus_realize(sbd, &error_fatal); 248 sysbus_mmio_map(sbd, 0, BBRAM_ADDR); 249 sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]); 250 } 251 252 static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) 253 { 254 Object *bits = OBJECT(&s->efuse); 255 Object *ctrl = OBJECT(&s->efuse_ctrl); 256 SysBusDevice *sbd; 257 258 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl, 259 TYPE_XLNX_ZYNQMP_EFUSE); 260 261 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, 262 sizeof(s->efuse), 263 TYPE_XLNX_EFUSE, &error_abort, 264 "efuse-nr", "3", 265 "efuse-size", "2048", 266 NULL); 267 268 qdev_realize(DEVICE(bits), NULL, &error_abort); 269 object_property_set_link(ctrl, "efuse", bits, &error_abort); 270 271 sbd = SYS_BUS_DEVICE(ctrl); 272 sysbus_realize(sbd, &error_abort); 273 sysbus_mmio_map(sbd, 0, EFUSE_ADDR); 274 sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); 275 } 276 277 static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) 278 { 279 static const struct UnimpInfo { 280 const char *name; 281 hwaddr base; 282 hwaddr size; 283 } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { 284 { .name = "apu", APU_ADDR, APU_SIZE }, 285 }; 286 unsigned int nr; 287 288 for (nr = 0; nr < ARRAY_SIZE(unimp_areas); nr++) { 289 const struct UnimpInfo *info = &unimp_areas[nr]; 290 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 291 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 292 293 assert(info->name && info->base && info->size > 0); 294 qdev_prop_set_string(dev, "name", info->name); 295 qdev_prop_set_uint64(dev, "size", info->size); 296 object_property_add_child(OBJECT(s), info->name, OBJECT(dev)); 297 298 sysbus_realize_and_unref(sbd, &error_fatal); 299 sysbus_mmio_map(sbd, 0, info->base); 300 } 301 } 302 303 static void xlnx_zynqmp_init(Object *obj) 304 { 305 MachineState *ms = MACHINE(qdev_get_machine()); 306 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 307 int i; 308 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 309 310 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, 311 TYPE_CPU_CLUSTER); 312 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); 313 314 for (i = 0; i < num_apus; i++) { 315 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", 316 &s->apu_cpu[i], 317 ARM_CPU_TYPE_NAME("cortex-a53")); 318 } 319 320 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); 321 322 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 323 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); 324 } 325 326 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 327 object_initialize_child(obj, "uart[*]", &s->uart[i], 328 TYPE_CADENCE_UART); 329 } 330 331 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { 332 object_initialize_child(obj, "can[*]", &s->can[i], 333 TYPE_XLNX_ZYNQMP_CAN); 334 } 335 336 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); 337 338 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 339 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i], 340 TYPE_SYSBUS_SDHCI); 341 } 342 343 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 344 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS); 345 } 346 347 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS); 348 349 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP); 350 351 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA); 352 353 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI); 354 355 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC); 356 357 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 358 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA); 359 } 360 361 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 362 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA); 363 } 364 365 object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA); 366 object_initialize_child(obj, "qspi-irq-orgate", 367 &s->qspi_irq_orgate, TYPE_OR_IRQ); 368 } 369 370 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 371 { 372 MachineState *ms = MACHINE(qdev_get_machine()); 373 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 374 MemoryRegion *system_memory = get_system_memory(); 375 uint8_t i; 376 uint64_t ram_size; 377 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 378 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 379 ram_addr_t ddr_low_size, ddr_high_size; 380 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 381 Error *err = NULL; 382 383 ram_size = memory_region_size(s->ddr_ram); 384 385 /* 386 * Create the DDR Memory Regions. User friendly checks should happen at 387 * the board level 388 */ 389 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 390 /* 391 * The RAM size is above the maximum available for the low DDR. 392 * Create the high DDR memory region as well. 393 */ 394 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 395 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 396 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 397 398 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev), 399 "ddr-ram-high", s->ddr_ram, ddr_low_size, 400 ddr_high_size); 401 memory_region_add_subregion(get_system_memory(), 402 XLNX_ZYNQMP_HIGH_RAM_START, 403 &s->ddr_ram_high); 404 } else { 405 /* RAM must be non-zero */ 406 assert(ram_size); 407 ddr_low_size = ram_size; 408 } 409 410 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low", 411 s->ddr_ram, 0, ddr_low_size); 412 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 413 414 /* Create the four OCM banks */ 415 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 416 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 417 418 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 419 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 420 memory_region_add_subregion(get_system_memory(), 421 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 422 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 423 &s->ocm_ram[i]); 424 425 g_free(ocm_name); 426 } 427 428 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 429 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 430 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 431 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); 432 qdev_prop_set_bit(DEVICE(&s->gic), 433 "has-virtualization-extensions", s->virt); 434 435 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); 436 437 /* Realize APUs before realizing the GIC. KVM requires this. */ 438 for (i = 0; i < num_apus; i++) { 439 const char *name; 440 441 object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit", 442 QEMU_PSCI_CONDUIT_SMC, &error_abort); 443 444 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 445 if (strcmp(name, boot_cpu)) { 446 /* Secondary CPUs start in PSCI powered-down state */ 447 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 448 "start-powered-off", true, &error_abort); 449 } else { 450 s->boot_cpu_ptr = &s->apu_cpu[i]; 451 } 452 453 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure, 454 NULL); 455 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt, 456 NULL); 457 object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar", 458 GIC_BASE_ADDR, &error_abort); 459 object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count", 460 num_apus, &error_abort); 461 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) { 462 return; 463 } 464 } 465 466 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 467 return; 468 } 469 470 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 471 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 472 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 473 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 474 MemoryRegion *mr; 475 uint32_t addr = r->address; 476 int j; 477 478 if (r->virt && !s->virt) { 479 continue; 480 } 481 482 mr = sysbus_mmio_get_region(gic, r->region_index); 483 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 484 MemoryRegion *alias = &s->gic_mr[i][j]; 485 486 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 487 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); 488 memory_region_add_subregion(system_memory, addr, alias); 489 490 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 491 } 492 } 493 494 for (i = 0; i < num_apus; i++) { 495 qemu_irq irq; 496 497 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 498 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 499 ARM_CPU_IRQ)); 500 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, 501 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 502 ARM_CPU_FIQ)); 503 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, 504 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 505 ARM_CPU_VIRQ)); 506 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, 507 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 508 ARM_CPU_VFIQ)); 509 irq = qdev_get_gpio_in(DEVICE(&s->gic), 510 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 511 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); 512 irq = qdev_get_gpio_in(DEVICE(&s->gic), 513 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 514 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); 515 irq = qdev_get_gpio_in(DEVICE(&s->gic), 516 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); 517 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); 518 irq = qdev_get_gpio_in(DEVICE(&s->gic), 519 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); 520 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); 521 522 if (s->virt) { 523 irq = qdev_get_gpio_in(DEVICE(&s->gic), 524 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); 525 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); 526 } 527 } 528 529 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); 530 if (err) { 531 error_propagate(errp, err); 532 return; 533 } 534 535 if (!s->boot_cpu_ptr) { 536 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 537 return; 538 } 539 540 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 541 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 542 } 543 544 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 545 NICInfo *nd = &nd_table[i]; 546 547 /* FIXME use qdev NIC properties instead of nd_table[] */ 548 if (nd->used) { 549 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 550 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 551 } 552 object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, 553 &error_abort); 554 object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23, 555 &error_abort); 556 object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, 557 &error_abort); 558 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { 559 return; 560 } 561 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 562 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 563 gic_spi[gem_intr[i]]); 564 } 565 566 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 567 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 568 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 569 return; 570 } 571 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 572 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 573 gic_spi[uart_intr[i]]); 574 } 575 576 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { 577 object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq", 578 XLNX_ZYNQMP_CAN_REF_CLK, &error_abort); 579 580 object_property_set_link(OBJECT(&s->can[i]), "canbus", 581 OBJECT(s->canbus[i]), &error_fatal); 582 583 sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); 584 if (err) { 585 error_propagate(errp, err); 586 return; 587 } 588 sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); 589 sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, 590 gic_spi[can_intr[i]]); 591 } 592 593 object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, 594 &error_abort); 595 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { 596 return; 597 } 598 599 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 600 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 601 602 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 603 char *bus_name; 604 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 605 Object *sdhci = OBJECT(&s->sdhci[i]); 606 607 /* 608 * Compatible with: 609 * - SD Host Controller Specification Version 3.00 610 * - SDIO Specification Version 3.0 611 * - eMMC Specification Version 4.51 612 */ 613 if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) { 614 return; 615 } 616 if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, 617 errp)) { 618 return; 619 } 620 if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) { 621 return; 622 } 623 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) { 624 return; 625 } 626 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 627 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 628 629 /* Alias controller SD bus to the SoC itself */ 630 bus_name = g_strdup_printf("sd-bus%d", i); 631 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus"); 632 g_free(bus_name); 633 } 634 635 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 636 gchar *bus_name; 637 638 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 639 return; 640 } 641 642 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 643 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 644 gic_spi[spi_intr[i]]); 645 646 /* Alias controller SPI bus to the SoC itself */ 647 bus_name = g_strdup_printf("spi%d", i); 648 object_property_add_alias(OBJECT(s), bus_name, 649 OBJECT(&s->spi[i]), "spi0"); 650 g_free(bus_name); 651 } 652 653 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) { 654 return; 655 } 656 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 657 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 658 659 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) { 660 return; 661 } 662 object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma), 663 &error_abort); 664 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 665 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 666 667 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) { 668 return; 669 } 670 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 671 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 672 673 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 674 return; 675 } 676 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 677 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 678 679 xlnx_zynqmp_create_bbram(s, gic_spi); 680 xlnx_zynqmp_create_efuse(s, gic_spi); 681 xlnx_zynqmp_create_unimp_mmio(s); 682 683 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 684 if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, 685 errp)) { 686 return; 687 } 688 if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma", 689 OBJECT(system_memory), errp)) { 690 return; 691 } 692 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) { 693 return; 694 } 695 696 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 697 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 698 gic_spi[gdma_ch_intr[i]]); 699 } 700 701 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 702 if (!object_property_set_link(OBJECT(&s->adma[i]), "dma", 703 OBJECT(system_memory), errp)) { 704 return; 705 } 706 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) { 707 return; 708 } 709 710 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 711 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 712 gic_spi[adma_ch_intr[i]]); 713 } 714 715 object_property_set_int(OBJECT(&s->qspi_irq_orgate), 716 "num-lines", NUM_QSPI_IRQ_LINES, &error_fatal); 717 qdev_realize(DEVICE(&s->qspi_irq_orgate), NULL, &error_fatal); 718 qdev_connect_gpio_out(DEVICE(&s->qspi_irq_orgate), 0, gic_spi[QSPI_IRQ]); 719 720 if (!object_property_set_link(OBJECT(&s->qspi_dma), "dma", 721 OBJECT(system_memory), errp)) { 722 return; 723 } 724 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) { 725 return; 726 } 727 728 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR); 729 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, 730 qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 0)); 731 732 if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", 733 OBJECT(&s->qspi_dma), errp)) { 734 return; 735 } 736 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) { 737 return; 738 } 739 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 740 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 741 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, 742 qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 1)); 743 744 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 745 g_autofree gchar *bus_name = g_strdup_printf("qspi%d", i); 746 g_autofree gchar *target_bus = g_strdup_printf("spi%d", i); 747 748 /* Alias controller SPI bus to the SoC itself */ 749 object_property_add_alias(OBJECT(s), bus_name, 750 OBJECT(&s->qspi), target_bus); 751 } 752 } 753 754 static Property xlnx_zynqmp_props[] = { 755 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 756 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 757 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 758 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 759 MemoryRegion *), 760 DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, 761 CanBusState *), 762 DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, 763 CanBusState *), 764 DEFINE_PROP_END_OF_LIST() 765 }; 766 767 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 768 { 769 DeviceClass *dc = DEVICE_CLASS(oc); 770 771 device_class_set_props(dc, xlnx_zynqmp_props); 772 dc->realize = xlnx_zynqmp_realize; 773 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 774 dc->user_creatable = false; 775 } 776 777 static const TypeInfo xlnx_zynqmp_type_info = { 778 .name = TYPE_XLNX_ZYNQMP, 779 .parent = TYPE_DEVICE, 780 .instance_size = sizeof(XlnxZynqMPState), 781 .instance_init = xlnx_zynqmp_init, 782 .class_init = xlnx_zynqmp_class_init, 783 }; 784 785 static void xlnx_zynqmp_register_types(void) 786 { 787 type_register_static(&xlnx_zynqmp_type_info); 788 } 789 790 type_init(xlnx_zynqmp_register_types) 791