1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "hw/boards.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/kvm.h" 27 #include "sysemu/sysemu.h" 28 #include "kvm_arm.h" 29 30 #define GIC_NUM_SPI_INTR 160 31 32 #define ARM_PHYS_TIMER_PPI 30 33 #define ARM_VIRT_TIMER_PPI 27 34 #define ARM_HYP_TIMER_PPI 26 35 #define ARM_SEC_TIMER_PPI 29 36 #define GIC_MAINTENANCE_PPI 25 37 38 #define GEM_REVISION 0x40070106 39 40 #define GIC_BASE_ADDR 0xf9000000 41 #define GIC_DIST_ADDR 0xf9010000 42 #define GIC_CPU_ADDR 0xf9020000 43 #define GIC_VIFACE_ADDR 0xf9040000 44 #define GIC_VCPU_ADDR 0xf9060000 45 46 #define SATA_INTR 133 47 #define SATA_ADDR 0xFD0C0000 48 #define SATA_NUM_PORTS 2 49 50 #define QSPI_ADDR 0xff0f0000 51 #define LQSPI_ADDR 0xc0000000 52 #define QSPI_IRQ 15 53 54 #define DP_ADDR 0xfd4a0000 55 #define DP_IRQ 113 56 57 #define DPDMA_ADDR 0xfd4c0000 58 #define DPDMA_IRQ 116 59 60 #define IPI_ADDR 0xFF300000 61 #define IPI_IRQ 64 62 63 #define RTC_ADDR 0xffa60000 64 #define RTC_IRQ 26 65 66 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 67 68 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 69 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 70 }; 71 72 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 73 57, 59, 61, 63, 74 }; 75 76 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 77 0xFF000000, 0xFF010000, 78 }; 79 80 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 81 21, 22, 82 }; 83 84 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 85 0xFF160000, 0xFF170000, 86 }; 87 88 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 89 48, 49, 90 }; 91 92 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 93 0xFF040000, 0xFF050000, 94 }; 95 96 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 97 19, 20, 98 }; 99 100 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 101 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 102 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 103 }; 104 105 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 106 124, 125, 126, 127, 128, 129, 130, 131 107 }; 108 109 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 110 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 111 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 112 }; 113 114 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 115 77, 78, 79, 80, 81, 82, 83, 84 116 }; 117 118 typedef struct XlnxZynqMPGICRegion { 119 int region_index; 120 uint32_t address; 121 uint32_t offset; 122 bool virt; 123 } XlnxZynqMPGICRegion; 124 125 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 126 /* Distributor */ 127 { 128 .region_index = 0, 129 .address = GIC_DIST_ADDR, 130 .offset = 0, 131 .virt = false 132 }, 133 134 /* CPU interface */ 135 { 136 .region_index = 1, 137 .address = GIC_CPU_ADDR, 138 .offset = 0, 139 .virt = false 140 }, 141 { 142 .region_index = 1, 143 .address = GIC_CPU_ADDR + 0x10000, 144 .offset = 0x1000, 145 .virt = false 146 }, 147 148 /* Virtual interface */ 149 { 150 .region_index = 2, 151 .address = GIC_VIFACE_ADDR, 152 .offset = 0, 153 .virt = true 154 }, 155 156 /* Virtual CPU interface */ 157 { 158 .region_index = 3, 159 .address = GIC_VCPU_ADDR, 160 .offset = 0, 161 .virt = true 162 }, 163 { 164 .region_index = 3, 165 .address = GIC_VCPU_ADDR + 0x10000, 166 .offset = 0x1000, 167 .virt = true 168 }, 169 }; 170 171 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 172 { 173 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 174 } 175 176 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, 177 const char *boot_cpu, Error **errp) 178 { 179 Error *err = NULL; 180 int i; 181 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, 182 XLNX_ZYNQMP_NUM_RPU_CPUS); 183 184 if (num_rpus <= 0) { 185 /* Don't create rpu-cluster object if there's nothing to put in it */ 186 return; 187 } 188 189 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, 190 TYPE_CPU_CLUSTER); 191 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); 192 193 for (i = 0; i < num_rpus; i++) { 194 char *name; 195 196 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", 197 &s->rpu_cpu[i], 198 ARM_CPU_TYPE_NAME("cortex-r5f")); 199 200 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 201 if (strcmp(name, boot_cpu)) { 202 /* Secondary CPUs start in PSCI powered-down state */ 203 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 204 "start-powered-off", &error_abort); 205 } else { 206 s->boot_cpu_ptr = &s->rpu_cpu[i]; 207 } 208 g_free(name); 209 210 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 211 &error_abort); 212 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 213 &err); 214 if (err) { 215 error_propagate(errp, err); 216 return; 217 } 218 } 219 220 qdev_init_nofail(DEVICE(&s->rpu_cluster)); 221 } 222 223 static void xlnx_zynqmp_init(Object *obj) 224 { 225 MachineState *ms = MACHINE(qdev_get_machine()); 226 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 227 int i; 228 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 229 230 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, 231 TYPE_CPU_CLUSTER); 232 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); 233 234 for (i = 0; i < num_apus; i++) { 235 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", 236 &s->apu_cpu[i], 237 ARM_CPU_TYPE_NAME("cortex-a53")); 238 } 239 240 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), 241 gic_class_name()); 242 243 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 244 sysbus_init_child_obj(obj, "gem[*]", &s->gem[i], sizeof(s->gem[i]), 245 TYPE_CADENCE_GEM); 246 } 247 248 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 249 sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]), 250 TYPE_CADENCE_UART); 251 } 252 253 sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), 254 TYPE_SYSBUS_AHCI); 255 256 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 257 sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci[i], 258 sizeof(s->sdhci[i]), TYPE_SYSBUS_SDHCI); 259 } 260 261 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 262 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), 263 TYPE_XILINX_SPIPS); 264 } 265 266 sysbus_init_child_obj(obj, "qspi", &s->qspi, sizeof(s->qspi), 267 TYPE_XLNX_ZYNQMP_QSPIPS); 268 269 sysbus_init_child_obj(obj, "xxxdp", &s->dp, sizeof(s->dp), TYPE_XLNX_DP); 270 271 sysbus_init_child_obj(obj, "dp-dma", &s->dpdma, sizeof(s->dpdma), 272 TYPE_XLNX_DPDMA); 273 274 sysbus_init_child_obj(obj, "ipi", &s->ipi, sizeof(s->ipi), 275 TYPE_XLNX_ZYNQMP_IPI); 276 277 sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc), 278 TYPE_XLNX_ZYNQMP_RTC); 279 280 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 281 sysbus_init_child_obj(obj, "gdma[*]", &s->gdma[i], sizeof(s->gdma[i]), 282 TYPE_XLNX_ZDMA); 283 } 284 285 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 286 sysbus_init_child_obj(obj, "adma[*]", &s->adma[i], sizeof(s->adma[i]), 287 TYPE_XLNX_ZDMA); 288 } 289 } 290 291 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 292 { 293 MachineState *ms = MACHINE(qdev_get_machine()); 294 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 295 MemoryRegion *system_memory = get_system_memory(); 296 uint8_t i; 297 uint64_t ram_size; 298 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 299 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 300 ram_addr_t ddr_low_size, ddr_high_size; 301 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 302 Error *err = NULL; 303 304 ram_size = memory_region_size(s->ddr_ram); 305 306 /* Create the DDR Memory Regions. User friendly checks should happen at 307 * the board level 308 */ 309 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 310 /* The RAM size is above the maximum available for the low DDR. 311 * Create the high DDR memory region as well. 312 */ 313 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 314 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 315 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 316 317 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev), 318 "ddr-ram-high", s->ddr_ram, ddr_low_size, 319 ddr_high_size); 320 memory_region_add_subregion(get_system_memory(), 321 XLNX_ZYNQMP_HIGH_RAM_START, 322 &s->ddr_ram_high); 323 } else { 324 /* RAM must be non-zero */ 325 assert(ram_size); 326 ddr_low_size = ram_size; 327 } 328 329 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low", 330 s->ddr_ram, 0, ddr_low_size); 331 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 332 333 /* Create the four OCM banks */ 334 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 335 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 336 337 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 338 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 339 memory_region_add_subregion(get_system_memory(), 340 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 341 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 342 &s->ocm_ram[i]); 343 344 g_free(ocm_name); 345 } 346 347 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 348 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 349 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 350 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); 351 qdev_prop_set_bit(DEVICE(&s->gic), 352 "has-virtualization-extensions", s->virt); 353 354 qdev_init_nofail(DEVICE(&s->apu_cluster)); 355 356 /* Realize APUs before realizing the GIC. KVM requires this. */ 357 for (i = 0; i < num_apus; i++) { 358 char *name; 359 360 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 361 "psci-conduit", &error_abort); 362 363 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 364 if (strcmp(name, boot_cpu)) { 365 /* Secondary CPUs start in PSCI powered-down state */ 366 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 367 "start-powered-off", &error_abort); 368 } else { 369 s->boot_cpu_ptr = &s->apu_cpu[i]; 370 } 371 g_free(name); 372 373 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 374 s->secure, "has_el3", NULL); 375 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 376 s->virt, "has_el2", NULL); 377 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 378 "reset-cbar", &error_abort); 379 object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus, 380 "core-count", &error_abort); 381 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 382 &err); 383 if (err) { 384 error_propagate(errp, err); 385 return; 386 } 387 } 388 389 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 390 if (err) { 391 error_propagate(errp, err); 392 return; 393 } 394 395 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 396 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 397 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 398 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 399 MemoryRegion *mr; 400 uint32_t addr = r->address; 401 int j; 402 403 if (r->virt && !s->virt) { 404 continue; 405 } 406 407 mr = sysbus_mmio_get_region(gic, r->region_index); 408 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 409 MemoryRegion *alias = &s->gic_mr[i][j]; 410 411 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 412 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); 413 memory_region_add_subregion(system_memory, addr, alias); 414 415 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 416 } 417 } 418 419 for (i = 0; i < num_apus; i++) { 420 qemu_irq irq; 421 422 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 423 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 424 ARM_CPU_IRQ)); 425 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, 426 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 427 ARM_CPU_FIQ)); 428 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, 429 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 430 ARM_CPU_VIRQ)); 431 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, 432 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 433 ARM_CPU_VFIQ)); 434 irq = qdev_get_gpio_in(DEVICE(&s->gic), 435 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 436 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); 437 irq = qdev_get_gpio_in(DEVICE(&s->gic), 438 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 439 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); 440 irq = qdev_get_gpio_in(DEVICE(&s->gic), 441 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); 442 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); 443 irq = qdev_get_gpio_in(DEVICE(&s->gic), 444 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); 445 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); 446 447 if (s->virt) { 448 irq = qdev_get_gpio_in(DEVICE(&s->gic), 449 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); 450 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); 451 } 452 } 453 454 if (s->has_rpu) { 455 info_report("The 'has_rpu' property is no longer required, to use the " 456 "RPUs just use -smp 6."); 457 } 458 459 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); 460 if (err) { 461 error_propagate(errp, err); 462 return; 463 } 464 465 if (!s->boot_cpu_ptr) { 466 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 467 return; 468 } 469 470 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 471 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 472 } 473 474 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 475 NICInfo *nd = &nd_table[i]; 476 477 if (nd->used) { 478 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 479 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 480 } 481 object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", 482 &error_abort); 483 object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", 484 &error_abort); 485 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 486 if (err) { 487 error_propagate(errp, err); 488 return; 489 } 490 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 491 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 492 gic_spi[gem_intr[i]]); 493 } 494 495 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 496 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 497 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 498 if (err) { 499 error_propagate(errp, err); 500 return; 501 } 502 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 503 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 504 gic_spi[uart_intr[i]]); 505 } 506 507 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 508 &error_abort); 509 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 510 if (err) { 511 error_propagate(errp, err); 512 return; 513 } 514 515 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 516 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 517 518 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 519 char *bus_name; 520 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 521 Object *sdhci = OBJECT(&s->sdhci[i]); 522 523 /* Compatible with: 524 * - SD Host Controller Specification Version 3.00 525 * - SDIO Specification Version 3.0 526 * - eMMC Specification Version 4.51 527 */ 528 object_property_set_uint(sdhci, 3, "sd-spec-version", &err); 529 if (err) { 530 error_propagate(errp, err); 531 return; 532 } 533 object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err); 534 if (err) { 535 error_propagate(errp, err); 536 return; 537 } 538 object_property_set_uint(sdhci, UHS_I, "uhs", &err); 539 if (err) { 540 error_propagate(errp, err); 541 return; 542 } 543 object_property_set_bool(sdhci, true, "realized", &err); 544 if (err) { 545 error_propagate(errp, err); 546 return; 547 } 548 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 549 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 550 551 /* Alias controller SD bus to the SoC itself */ 552 bus_name = g_strdup_printf("sd-bus%d", i); 553 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus"); 554 g_free(bus_name); 555 } 556 557 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 558 gchar *bus_name; 559 560 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 561 if (err) { 562 error_propagate(errp, err); 563 return; 564 } 565 566 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 567 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 568 gic_spi[spi_intr[i]]); 569 570 /* Alias controller SPI bus to the SoC itself */ 571 bus_name = g_strdup_printf("spi%d", i); 572 object_property_add_alias(OBJECT(s), bus_name, 573 OBJECT(&s->spi[i]), "spi0"); 574 g_free(bus_name); 575 } 576 577 object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); 578 if (err) { 579 error_propagate(errp, err); 580 return; 581 } 582 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 583 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 584 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); 585 586 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 587 gchar *bus_name; 588 gchar *target_bus; 589 590 /* Alias controller SPI bus to the SoC itself */ 591 bus_name = g_strdup_printf("qspi%d", i); 592 target_bus = g_strdup_printf("spi%d", i); 593 object_property_add_alias(OBJECT(s), bus_name, 594 OBJECT(&s->qspi), target_bus); 595 g_free(bus_name); 596 g_free(target_bus); 597 } 598 599 object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); 600 if (err) { 601 error_propagate(errp, err); 602 return; 603 } 604 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 605 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 606 607 object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err); 608 if (err) { 609 error_propagate(errp, err); 610 return; 611 } 612 object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", 613 &error_abort); 614 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 615 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 616 617 object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err); 618 if (err) { 619 error_propagate(errp, err); 620 return; 621 } 622 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 623 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 624 625 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 626 if (err) { 627 error_propagate(errp, err); 628 return; 629 } 630 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 631 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 632 633 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 634 object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err); 635 if (err) { 636 error_propagate(errp, err); 637 return; 638 } 639 object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err); 640 if (err) { 641 error_propagate(errp, err); 642 return; 643 } 644 645 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 646 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 647 gic_spi[gdma_ch_intr[i]]); 648 } 649 650 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 651 object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err); 652 if (err) { 653 error_propagate(errp, err); 654 return; 655 } 656 657 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 658 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 659 gic_spi[adma_ch_intr[i]]); 660 } 661 } 662 663 static Property xlnx_zynqmp_props[] = { 664 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 665 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 666 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 667 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 668 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 669 MemoryRegion *), 670 DEFINE_PROP_END_OF_LIST() 671 }; 672 673 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 674 { 675 DeviceClass *dc = DEVICE_CLASS(oc); 676 677 device_class_set_props(dc, xlnx_zynqmp_props); 678 dc->realize = xlnx_zynqmp_realize; 679 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 680 dc->user_creatable = false; 681 } 682 683 static const TypeInfo xlnx_zynqmp_type_info = { 684 .name = TYPE_XLNX_ZYNQMP, 685 .parent = TYPE_DEVICE, 686 .instance_size = sizeof(XlnxZynqMPState), 687 .instance_init = xlnx_zynqmp_init, 688 .class_init = xlnx_zynqmp_class_init, 689 }; 690 691 static void xlnx_zynqmp_register_types(void) 692 { 693 type_register_static(&xlnx_zynqmp_type_info); 694 } 695 696 type_init(xlnx_zynqmp_register_types) 697