xref: /qemu/hw/arm/xlnx-zynqmp.c (revision 7729e1f4b3c670eca38cc0ee0d96c1177efbc1e3)
1 /*
2  * Xilinx Zynq MPSoC emulation
3  *
4  * Copyright (C) 2015 Xilinx Inc
5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  */
17 
18 #include "hw/arm/xlnx-zynqmp.h"
19 #include "exec/address-spaces.h"
20 
21 #define GIC_NUM_SPI_INTR 160
22 
23 #define GIC_BASE_ADDR       0xf9000000
24 #define GIC_DIST_ADDR       0xf9010000
25 #define GIC_CPU_ADDR        0xf9020000
26 
27 typedef struct XlnxZynqMPGICRegion {
28     int region_index;
29     uint32_t address;
30 } XlnxZynqMPGICRegion;
31 
32 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
33     { .region_index = 0, .address = GIC_DIST_ADDR, },
34     { .region_index = 1, .address = GIC_CPU_ADDR,  },
35 };
36 
37 static void xlnx_zynqmp_init(Object *obj)
38 {
39     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
40     int i;
41 
42     for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
43         object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
44                           "cortex-a53-" TYPE_ARM_CPU);
45         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
46                                   &error_abort);
47     }
48 
49     object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
50     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
51 }
52 
53 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
54 {
55     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
56     MemoryRegion *system_memory = get_system_memory();
57     uint8_t i;
58     Error *err = NULL;
59 
60     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
61     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
62     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS);
63     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
64     if (err) {
65         error_propagate((errp), (err));
66         return;
67     }
68     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
69     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
70         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
71         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
72         MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
73         uint32_t addr = r->address;
74         int j;
75 
76         sysbus_mmio_map(gic, r->region_index, addr);
77 
78         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
79             MemoryRegion *alias = &s->gic_mr[i][j];
80 
81             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
82             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
83                                      0, XLNX_ZYNQMP_GIC_REGION_SIZE);
84             memory_region_add_subregion(system_memory, addr, alias);
85         }
86     }
87 
88     for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
89         object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
90                                 "psci-conduit", &error_abort);
91         if (i > 0) {
92             /* Secondary CPUs start in PSCI powered-down state */
93             object_property_set_bool(OBJECT(&s->cpu[i]), true,
94                                      "start-powered-off", &error_abort);
95         }
96 
97         object_property_set_int(OBJECT(&s->cpu[i]), GIC_BASE_ADDR,
98                                 "reset-cbar", &err);
99         if (err) {
100             error_propagate((errp), (err));
101             return;
102         }
103 
104         object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
105         if (err) {
106             error_propagate((errp), (err));
107             return;
108         }
109 
110         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
111                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
112     }
113 }
114 
115 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
116 {
117     DeviceClass *dc = DEVICE_CLASS(oc);
118 
119     dc->realize = xlnx_zynqmp_realize;
120 }
121 
122 static const TypeInfo xlnx_zynqmp_type_info = {
123     .name = TYPE_XLNX_ZYNQMP,
124     .parent = TYPE_DEVICE,
125     .instance_size = sizeof(XlnxZynqMPState),
126     .instance_init = xlnx_zynqmp_init,
127     .class_init = xlnx_zynqmp_class_init,
128 };
129 
130 static void xlnx_zynqmp_register_types(void)
131 {
132     type_register_static(&xlnx_zynqmp_type_info);
133 }
134 
135 type_init(xlnx_zynqmp_register_types)
136